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Patent # Description
US-6,880,120 Sequence-based verification method and system
A hardware verification method includes obtaining a set of packets to be driven by a device under test and obtaining a set of timing and relation criteria which...
US-6,880,118 System and method for testing operational transmissions of an integrated circuit
A source synchronous test methodology and apparatus. In one embodiment, an integrated circuit (IC) configured for source synchronous I/O transactions may be a...
US-6,880,071 Selective signalling of later reserve location memory fault in compound compare and swap
A sequentially performed implementation of a compound compare-and-swap (nCAS) operation has been developed. In one implementation, a double compare-and-swap...
US-6,880,060 Method for storing metadata in a physical sector
A method for embedding integrity metadata. In one exemplary embodiment, a plurality of integrity metadata segments is determined. Each integrity metadata segment...
US-6,880,057 Split write data processing mechanism for memory controllers utilizing inactive periods during write data...
A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write...
US-6,880,028 Dynamic request priority arbitration
A system and method are provided for dynamically determining the priority of requests for access to a resource taking into account changes in the access needs of...
US-6,879,995 Application server message logging
System and method for performing message logging for networked applications running on application servers. The application server may run a process referred to...
US-6,879,929 Sense amplifier thermal correction scheme
A system and method of adjusting a sense amplifier includes providing an amplification control parameter to the sense amplifier. A temperature of the sense...
US-6,879,328 Support of multi-layer transparency
A system and method for generating graphics images from 3-dimensional graphics data representing one or more transparent objects and one or more opaque objects...
US-6,878,874 Electronics assembly
A chassis for an electronic system. The chassis includes a recess therein for housing a plurality of cooling fans that are arranged in series and can be removed...
US-6,877,264 Universal snap-in-place customer label plate
A label holder for labeling a rack-mounted computer system component is provided. The label holder includes an elongated body, a plurality of legs, and at least...
US-6,877,204 Riveting method
A method of joining a plurality of sheets by means of a blind rivet, comprises: (i) forming holes in the sheets and placing the sheets together so that the ...
US-D503,932 Radio
US-6,877,163 Method and system for dynamic proxy classes
In an object-oriented data processing system, methods and systems in accordance with the present invention provide a proxy class dynamically generated at runtime...
US-6,877,111 Method and apparatus for managing replicated and migration capable session state for a Java platform
An invention is disclosed managing the replicated and migration capable state for an enterprise Java bean (EJB) application. The invention includes executing a...
US-6,877,108 Method and apparatus for providing error isolation in a multi-domain computer system
A method and apparatus for providing error isolation in a multi-domain computer system. The system includes a plurality of system resources allocated to form at...
US-6,877,098 System and method for directing access from a framebuffer to a virtual framebuffer when the framebuffer is...
Methods and apparatus for managing power of a computer system. Access to a device by a process that accesses the device but does not require user interaction to...
US-6,877,094 Method and apparatus for authentication and payment for devices participating in Jini communities
Architectures that enable different types of security devices to operate interchangeably in very large network environments for authentication and metered access...
US-6,877,088 Methods and apparatus for controlling speculative execution of instructions based on a multiaccess memory condition
Mechanisms and techniques operate in a computerized device to enable or disable speculative execution of instructions such as reordering of load and store...
US-6,877,077 Memory controller and method using read and write queues and an ordering queue for dispatching read and write...
In one of the many embodiments disclosed herein, a method for dispatching read and write requests to a memory is disclosed which includes queuing at least one...
US-6,877,056 System with arbitration scheme supporting virtual address networks and having split ownership and access right...
A computer system may include several client devices, a data network configured to transmit data packets between the client devices, a coherency mode storage...
US-6,877,055 Method and apparatus for efficiently broadcasting transactions between a first address repeater and a second...
A computer system including a first repeater and a second repeater that is coupled to the first repeater. The computer system also includes a third repeater that...
US-6,877,026 Bulk import in a directory server
A method of bulk import in a directory server, including defining an extended operation on a server and a client, sending an extended operation request from the...
US-6,877,011 System and method for host based storage virtualization
The illustrative embodiment of the present invention provides a method of inserting a software created virtual interface between the user of a host electronic...
US-6,876,996 Method and apparatus for using a shared library mechanism to facilitate sharing of metadata
One embodiment of the present invention provides a system that uses a shared library to facilitate sharing objects containing metadata. During operation, the...
US-6,876,230 Synchronous clocked full-rail differential logic with single-rail logic and shut-off
In a synchronous clocked full-rail differential logic circuit with single-rail logic and shut-off the complementary logic function of the prior art is replaced...
US-6,876,024 Method and layout for MOS capacitors with phase shifted layers
A layout and a method for generating a mask for a capacitor are provided. The layout and the mask allow for the formation of the capacitor or an array of...
US-D503,541 Paper product
US-6,874,145 Methods and apparatus for implementing an application lifecycle design for applications
Methods and apparatus for managing execution of an application according to an application lifecycle. The application lifecycle is managed by an application...
US-6,874,066 Caching mechanism for a virtual heap
A caching mechanism for a virtual persistent heap. A feature of a virtual persistent heap is the method used to cache portions of the virtual persistent heap...
US-6,874,012 System and method for a display device using a priority messaging protocol
A display device executing a network messaging protocol and capable of receiving display requests from multiple network devices communicating with the display...
US-6,873,980 System for interfacing an application program with diverse databases
A system for querying a database. Query strings comprising queries from application program are loaded from a text file into a query lookups table. The...
US-6,873,630 Method and apparatus for a multi-gigabit ethernet architecture
An Ethernet architecture is provided for connecting a computer system or other network entity to a dedicated Ethernet network medium. The network interface...
US-6,873,503 SSTL pull-up pre-driver design using regulated power supply
A SSTL memory interface pre-driver stage that uses a voltage regulator to generate a `virtual` ground reference voltage is provided. The `virtual` ground voltage...
US-6,873,459 Image transferring apparatus
An image transferring device is disclosed having a support plate, a reflective plate and a core member adapted to support the support plate and reflective plate...
US-6,873,330 System and method for performing predictable signature analysis
In one embodiment, a computer system includes a first component configured to output data on a bus in response to a request for data from a second component. The...
US-6,873,034 Solid-state imaging device, method for producing same, and mask
The present invention provides a solid-state imaging device comprising: a transparent substrate transmitting light therethrough; a first chip including a...
US-6,871,332 Structure and method for separating geometries in a design layout into multi-wide object classes
Manipulation of a multi-wide object class design layout to facilitate design rule checking or automatic correction of design rule errors is improved by deriving...
US-6,871,327 Method and apparatus for extending coverage of GUI tests
A method of testing a graphical user interface includes selecting a widget of the graphical user interface, associating an access mode with the widget,...
US-6,871,323 Interactive graphical user interface for television set-top box
A graphical user interface (GUI) for a television set-top box which includes a web browser. The set-top box has an Internet data connection and is controlled...
US-6,871,294 Dynamically reconfigurable interconnection
A method and apparatus for dynamically reconfiguring a computing system are disclosed. The method comprises detecting a predetermined condition triggering a...
US-6,871,290 Method for reducing a magnitude of a rate of current change of an integrated circuit
A method for reducing a magnitude of a rate of current change of an integrated circuit is provided. The method uses a plurality of transistors controlled by a...
US-6,871,219 Dynamic memory placement policies for NUMA architecture
A distributed shared memory multiprocessor computer system utilizes page placement policies to reduce data access latencies. Pages of memory are allocated to...
US-6,870,842 Using multicasting to provide ethernet-like communication behavior to selected peers on a network
Methods and systems consistent with the present invention provide a Supernet, a private network constructed out of components from a public-network...
US-6,870,789 Modified retirement payload array
In the Retirement Payload Array (RPA) of a microprocessor, the pointer advance signal "ADVANCE POINTER" from the Instruction Retirement Logic (IRL) of the...
US-6,870,781 Semiconductor device verification system and method
A semiconductor device verification system and method isolates errors detected during verification by comparing a predetermined stimulus applied to the...
US-6,870,775 System and method for small read only data
A system and method is provided for minimizing read-only data retrieval time and/or area through the use of combinatorial logic. In one embodiment of the present...
US-6,870,399 Bidirectional input/output cells
A bi-directional input/output (IO) cell for transmitting and receiving data signals simultaneously over a single line. The bidirectional IO cell having an IO...
US-6,870,271 Integrated circuit assembly module that supports capacitive communication between semiconductor dies
One embodiment of the present invention provides an integrated circuit assembly module, including a first semiconductor die and a second semiconductor die, each...
US-6,870,252 Chip packaging and connection for reduced EMI
A chip package for reduced EMI. In one embodiment, a chip package includes a semiconductor chip mounted on a substrate. First and second horizontal conductors...
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