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Patent # Description
US-D504,895 Computer housing
US-D504,882 Radio
US-6,889,343 Method and apparatus for verifying consistency between a first address repeater and a second address repeater
In a computer system having a first repeater and a second repeater, the first repeater coupled to the second repeater by a bus, the first repeater operable to...
US-6,889,329 Adding secure external virtual memory to smart cards
The Smart Card URL Programming interface (UPI) builds a local web or card server around a card terminal and the inserted smart card. This server can also support...
US-6,889,297 Methods and systems for eliminating data redundancies
Methods, systems, and articles of manufacture consistent with the present invention eliminate data redundancies. A first data block identifier is obtained for a...
US-6,889,277 System and method for dynamically tuning interrupt coalescing parameters
A system and method for dynamically tuning the interrupt coalescing behavior of a communication interface to suit the workload of the interface. An interrupt...
US-6,889,248 Automatically configuring a server into a master or slave server based on its relative position in a server network
A server network is described. In one embodiment, the server network comprises a global master server, a local master server and one or more slave servers. The...
US-6,889,227 Database access bridge system and process
A system or method enables a two tier computer application to operate in a three tier computer environment without specific programming for the three tier...
US-6,888,785 Fault tolerance mechanism for a storage device that stores data in stacks within an integral storage medium
In one embodiment, a storage device includes a controller, an integral storage medium that includes one or more stacks, where each stack includes multiple...
US-6,888,720 Distributed graphitic foam heat exchanger system
A system for cooling at least two electronic components comprises a plurality of graphitic foam products which are each thermally coupled to a corresponding...
US-6,888,506 Plate type antenna with dual channels
A plate type antenna for a small size mobile wireless communication device can be simultaneously to fit two different channels of 5.4 GH.sub.Z and 2.4 GH.sub.Z...
US-6,886,798 Support for electronics assembly
A support for holding an electronics assembly, comprises: (i) a rigid frame (6) that can be secured to the assembly; (ii) one or more cushioning elements (8) for...
US-6,886,378 Container locking system
A system for locking cargo containers. The container locking system comprises a lock housing comprising a box, a lock bar housing disposed behind the lock...
US-6,886,157 Method and apparatus for creating efficient native methods that extend a bytecode interpreter
Methods, apparatus and computer program products are disclosed for a method of invoking a native method in a Java virtual machine ("JVM"). A special-purpose fast...
US-6,886,145 Reducing verification time for integrated circuit design including scan circuits
A testbench for an integrated circuit (IC) design including a chain of scan circuits having a memory characteristic is verified by: (a) dividing the chain of...
US-6,886,108 Threshold adjustment following forced failure of storage device
A storage device is monitored for data integrity errors and each detected data integrity error is stored in a count. When that count reaches a threshold limit,...
US-6,886,081 Method and tool for determining ownership of a multiple owner lock in multithreading environments
A method for determining an ownership of for a multiple owner lock. The method includes determining potential owners of the lock by inspecting a core file of a...
US-6,886,053 Method, system, and program for managing access to a device
Provided are a method, system, and program for selecting a path to a device to use when sending data requests to the device. Data requests are submitted to the...
US-6,886,031 Efficient connection and memory management for message passing on a single SMP or a cluster of SMPs
A method for efficient connection establishment and use for message passing on a single symmetric multiprocessor node or on a cluster of symmetric multiprocessor...
US-6,885,610 Programmable delay for self-timed-margin
A system and method for adjusting the clock delay in a self-timed memory system having a memory array and a sense amplifier includes a programmable delay circuit...
US-6,885,384 Method of creating a larger 2-D sample location pattern from a smaller one by means of X, Y address permutation
A system and method are disclosed for reproducing a pre-selected larger 2-D sample location pattern from a smaller one by means of X,Y address permutation. This...
US-6,885,375 Stalling pipelines in large designs
A method and a system for stalling large pipelined designs. A computational pipeline may comprise a first module and a second module coupled together. The first...
US-6,885,361 Tactile feedback mechanism for a data processing system
An apparatus for providing a tactile stimulus to a part of the body of a physical operator when a virtual operator, created by movements of the physical...
US-6,883,716 Secure photo carrying identification device, as well as means and method for authenticating such an...
Means and a method for authenticating a photographic image (3) on an identification device (1), the identification device (1) being provided with: a photographic...
US-6,883,355 High security combination padlock with locking bar
By forming a combination padlock from heavy duty metal throughout with an enlarged, heavy duty locking bar or shackle being employed having a tamper-proof...
US-D504,531 Rechargeable light
US-D504,425 Computer housing
US-6,883,163 Populating resource-constrained devices with content verified using API definitions
Remote incremental program verification may be achieved by receiving content verified by at least one content provider, installing the content on a...
US-6,883,162 Annotations for transaction tracing
A method and mechanism for annotating a transaction stream. A processing unit is configured to generate annotation transactions which are inserted into a...
US-6,883,149 Via enclosure rule check in a multi-wide object class design layout
In a multi-wide class design layout, design rule checks for enclosure of multi wide class objects prevent false errors or false passes by performing such checks...
US-6,883,131 XOR processing incorporating error correction code data protection
A method for operating a data processing system is provided. The method includes receiving a plurality of data segments, and for each of the plurality of data...
US-6,883,108 Fault-tolerant routing scheme for a multi-path interconnection fabric in a storage network
Embodiments of a routing system are disclosed, including a method for routing a plurality of communications in a storage system. The storage system may include a...
US-6,883,100 Method and system for dynamic issuance of group certificates
In accordance with the invention, on-line group servers issue group membership or group non-membership certificates upon request. Furthermore, when a requester...
US-6,883,074 System and method for efficient write operations for repeated snapshots by copying-on-write to most recent snapshot
An embodiment of the invention provides a method for improving efficiency in a system containing repeated snapshots of an original data store. A READ/WRITE...
US-6,883,068 Methods and apparatus for implementing a chche replacement scheme
Methods and systems are provided for processing a cache. A candidate object is identified for updating. A fresh object corresponding to the candidate object is...
US-6,883,010 Facilitating failover to a secondary file server in a highly available file system
One embodiment of the present invention provides a system for elevating a secondary file server to act as a new primary file server in a highly available file...
US-6,883,006 Additions on circular singly linked lists
During a scan operation in a circular, singly linked list having a number of list entries each of which has an associated next pointer field and a root pointer...
US-6,882,649 Least choice first arbiter
In a system with multiple requesters making multiple requests for resources, an arbiter prioritizes requests based on the number of requests made by a requester....
US-6,882,645 Apparatus and method for sequencing memory operations in an asynchronous switch fabric
One embodiment of the present invention provides a system that facilitates implementing a memory mechanism within an asynchronous switch fabric. The system...
US-6,882,530 Integrated component rack and AC power distribution
A network system and computer component device rack having an integrated AC power distribution system is provided. The device rack and power distribution system...
US-6,882,354 Scroll bars with user feedback
A graphical user interface uses scroll bars having a single pixel width and a much larger scroll button or thumb. Both the scroll bar and the scroll button may...
US-6,882,196 Duty cycle corrector
A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay...
US-6,881,078 Interconnecting device that allows for connections in small space
An adapter for an interconnecting device. The adapter comprises a backboard having a first end and a second end. A connector having first conductive elements is...
US-6,880,970 Method and apparatus for isolating an ambient air temperature sensor
A method and apparatus for thermally isolating a temperature sensor mounted on a printed circuit board from a heat generating component mounted on the printed...
US-6,880,964 Chain-controlled lamp stand with multi-stage light modulation
A chain controlled lamp stand with multi-stage light modulation includes a control device to modulate brightness of a lamp. The control device consists of a...
US-6,880,155 Token-based linking
A system links architecture neutral code downloaded to a resource constrained computer. The code may be separated into one or more packages having one or more...
US-6,880,144 High speed low power bitline
A circuit for controlling a bitline during a memory access operation is provided. The circuit includes a plurality of sub-arrays with each sub-array having a...
US-6,880,139 Electromigration risk analysis in integrated circuit power interconnect systems using pseudo dynamic simulation
Methods of and apparatuses for performing electromigration risk analyses of power interconnect systems in integrated circuits employ a pseudo dynamic simulation...
US-6,880,120 Sequence-based verification method and system
A hardware verification method includes obtaining a set of packets to be driven by a device under test and obtaining a set of timing and relation criteria which...
US-6,880,118 System and method for testing operational transmissions of an integrated circuit
A source synchronous test methodology and apparatus. In one embodiment, an integrated circuit (IC) configured for source synchronous I/O transactions may be a...
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