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Patent # Description
US-6,944,860 Method and apparatus for representing and encapsulating active computing environments
The present invention provides a representation and encapsulation of active computing environments. In accordance with one or more embodiments of the present...
US-6,944,856 Method, system, program, and data structures for applying a patch to a computer system
Provided is a method, system, program, and data structure for applying a patch to a computer system, wherein the patch includes content to add to the computer. A...
US-6,944,811 Blockage aware zero skew clock routing method
A blockage aware zero skew clock routing method for calculating the distance, and therefore the delay, between two points takes into account any blockages along...
US-6,944,795 Method and apparatus for stabilizing GUI testing
A method for stabilizing an event queue during a graphical user interface test includes placing a test event on a tail of the event queue, generating a first...
US-6,944,788 System and method for enabling failover for an application server cluster
A system and method for enabling failover in an application server cluster. A "primary" application server computer in the cluster may provide a service or data...
US-6,944,761 Log-on service providing credential level change without loss of session continuity
A security architecture has been developed in which a single sign-on is provided for multiple information resources. Rather than specifying a single...
US-6,944,756 Controls for recursion at system startup
The present invention provides a method and apparatus for controlling recursion at system startup. The method comprises creating one or more levels of device...
US-6,944,738 Scalable design for DDR SDRAM buses
A memory subsystem and a method for use in accessing a memory system are disclosed. The memory subsystem comprising a plurality of SDRAM memory modules and a...
US-6,944,724 Method and apparatus for decoupling tag and data accesses in a cache memory
One embodiment of the present invention provides a system that decouples a tag access from a corresponding data access within a cache memory. The system operates...
US-6,944,722 Method and system for postmortem identification of falsely shared memory objects
A method for utilizing postmortem object type identification to identify falsely shared memory objects is disclosed. In one method embodiment, the present...
US-6,944,692 Automated calibration of I/O over a multi-variable eye window
A method and apparatus for automated calibration of I/O over a multi-variable eye window is provided. A transmitter may conduct data transmissions to a receiver...
US-6,944,666 Mechanism for enabling customized session managers to interact with a network server
A mechanism for enabling customized session managers to interact with a network server is disclosed. A programming interface enables customized session managers...
US-6,944,663 Method and apparatus for using client puzzles to protect against denial-of-service attacks
One embodiment of the present invention provides a system that protects a server against denial-of-service attacks. During operation, the server receives a...
US-6,944,278 Internet-activated callback service
Techniques for using the Internet to establish an international telephone call using a callback service where there is a rate difference between the source and...
US-6,944,185 Selectable depacketizer architecture
A scheme is provided that permits the use of a selectable depacketization module to depacketize data streams. An RTP session manager is responsible for receiving...
US-6,944,025 EMI shielding apparatus
An electromagnetic shielding structure is provided for a microprocessor or other electronic device that emits electromagnetic radiation. The structure includes a...
US-6,944,019 Integrity monitoring
A server blade may comprise a processor and a network interface. The network interface can be configured be connected to a network remote the server blade. The...
US-6,943,797 Early primitive assembly and screen-space culling for multiple chip graphics system
A multi-chip system and method are disclosed for incorporating a primitive assembler in each of one or more geometry chips and one or more rasterization chips....
US-6,943,796 Method of maintaining continuity of sample jitter pattern across clustered graphics accelerators
A system and method are disclosed to allow the tiling of sample jitter patterns to be independent of the tiling of clustered graphics accelerators. Each...
US-6,943,791 Z-slope test to optimize sample throughput
A system and method are disclosed for utilizing a Z slope test to select polygons that may be candidates for multiple storage methods. The method may calculate...
US-6,943,436 EMI heatspreader/lid for integrated circuit packages
An integrated circuit package includes a lid with EMI containment features. The lid may include a plurality of projections adapted to couple a ground plane of a...
US-6,942,338 Spectacle frame having user-replaceable arm
A spectacle frame has a frameless lens or lens frame, an arm, a clamp that bears upon the arm and is attached hingedly to an arm mounting of the frameless lens...
US-6,942,026 Fin assembly of heat sink
A fin assembly for a heat sink has a plurality of metal plates stacked with each other. Each metal plate has a body member and a plurality of connecting...
US-6,941,968 Fluid spigot and filter unit
A fluid spigot with a spigot body, a spigot tube, a rotary disc valve located in a valve cavity in the spigot body, the rotary disc valve having an opened and...
US-D509,450 Sport timer
US-D509,382 Eyeglass display
US-6,941,574 Interactive television system and method having on-demand web-like navigational capabilities for displaying...
A system and method for displaying still video images related to video content in an interactive broadcast television system. The system and method of the...
US-6,941,556 Method and system for type identification for multiple object interfaces in a distributed object environment
A system and method provides dynamic and static type support for multiple definitions of individual types in a distributed object environment. Fully scoped...
US-6,941,532 Clock skew verification methodology for grid-based design
A method and apparatus for determining clock insertion delays for a microprocessor design having a grid-based clock distribution. The method includes...
US-6,941,522 Methods and apparatus for implementing a progress reporting interface
Methods and apparatus for providing a progress associated with an executing process are disclosed. A progress report is generated in a progress reporting...
US-6,941,493 Memory subsystem including an error detection mechanism for address and control signals
A memory subsystem includes a memory controller coupled to a memory module including a plurality of memory chips via a memory bus. The memory controller may...
US-6,941,456 Method, system, and program for encrypting files in a computer system
Provided is a method, system, and program for encrypting files in a computer in communication with a volatile memory and non-volatile storage device. An...
US-6,941,451 Management subsystem and method for discovering management device functions
A management subsystem and method for discovering management device functions. A management subsystem includes a system controller coupled to a plurality of...
US-6,941,410 Virtual heap for a virtual machine
A virtual heap for a process executing within a virtual machine is described. In one embodiment, the virtual persistent heap may allow the running of an...
US-6,940,814 System and method for a quality of service in a multi-layer network element
A multi-layer network element for forwarding received packets from an input port to one or more output ports with quality of service. When output queues exceed...
US-6,940,771 Methods and circuits for balancing bitline precharge
A memory array design is provided. Memory cells are defined an intersections of rows and columns. A pair of bitline segments are defined for each column. A...
US-6,940,728 Circuit board retaining brackets
A mother board retaining bracket is mounted to an outer circuit board housing and supports an edge of a mother board. The mother board retaining bracket prevents...
US-6,940,529 Graphics system configured to perform distortion correction
A graphics system comprises pixel calculation units and a sample buffer which stores a two-dimensional field of samples. Each pixel calculation unit selects...
US-6,940,514 Parallel initialization path for rasterization engine
A system and method are disclosed for a rasterization pipeline with a parallel initialization path that may provide an increased rate of triangle processing. The...
US-6,939,376 Drug-delivery endovascular stent and method for treating restenosis
An intravascular stent and method for inhibiting restenosis, following vascular injury, is disclosed. The stent has an expandable, linked-filament body and a...
US-6,938,263 SYSTEM AND METHOD FOR FACILITATING DYNAMIC LOADING OF "STUB" INFORMATION TO ENABLE A PROGRAM OPERATING IN ONE...
A stub retrieval and loading subsystem is disclosed for use in connection with a remote method invocation system. The stub retrieval and loading subsystem...
US-6,938,247 Small memory footprint system and method for separating applications within a single virtual machine
A system and method for isolating the execution of a plurality of applications. The applications may utilize or share one or more "original" classes. Only one...
US-6,938,181 Field replaceable storage array
A single field replaceable storage or computer system may include a processor coupled to a peripheral bus by a bridge device. The field replaceable unit (FRU)...
US-6,938,169 Channel-specific file system views in a private network using a public-network infrastructure
Methods and systems consistent with the present invention provide a Supernet, a private network constructed out of components from a public-network...
US-6,938,147 Processor with multiple-thread, vertically-threaded pipeline
A processor reduces wasted cycle time resulting from stalling and idling, and increases the proportion of execution time, by supporting and implementing both...
US-6,938,134 System for storing block allocation information on multiple snapshots
An apparatus and method for locating free data blocks in a microprocessor-based system for which snapshots are maintained. The snapshots are stored periodically,...
US-6,938,130 Method and apparatus for delaying interfering accesses from other threads during transactional program execution
One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional...
US-6,938,119 DRAM power management
A system and method for limiting power consumption of a computer memory system. The system and method includes selecting a memory access rate. The selected...
US-6,938,085 Mechanism for enabling session information to be shared across multiple processes
A mechanism for enabling session information to be shared across multiple processes in a multi-process environment is disclosed. There is provided a shared...
US-6,937,971 System and method for determining the desired decoupling components for a power distribution system having a...
A system and method for determining the desired decoupling components for a power distribution system having a voltage regulator module. The system may employ a...
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