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Patent # Description
US-6,973,547 Coherence message prediction mechanism and multiprocessing computer system employing the same
A coherence prediction mechanism includes a history cache for storing a plurality of cache entries each storing coherence history information for a corresponding...
US-6,973,545 System with a directory based coherency protocol and split ownership and access right coherence mechanism
Various systems and methods for using a directory based coherency protocol in a system that employs a split ownership and access right cache coherence mechanism...
US-6,973,493 Mechanism and apparatus for security of newly spawned repository spaces in a distributed computing environment
A system and method for providing security for newly spawned spaces in a distributed computing environment. A client may access a first space service. The...
US-6,973,491 System and method for monitoring and managing system assets and asset configurations
A system and method for monitoring the configuration and/or status of target devices on a network. The system comprises a monitoring application that can be run...
US-6,973,480 Mechanism for implementing server-side pluglets
A server-centric approach is disclosed for enabling a browser to handle content types that it cannot inherently process. Rather than executing plug-ins on a...
US-6,973,465 Mechanism for migrating a file sequence with versioning information from one workspace to another
A mechanism is disclosed for migrating a file sequence from a first workspace managed by a first workspace management system into a second workspace managed by a...
US-6,973,463 Replication architecture for a directory server
A directory server includes a supplier server, a consumer server in communication with the supplier server, a plurality of pluggable services that manage...
US-6,973,412 Method and apparatus involving a hierarchy of field replaceable units containing stored data
Apparatus representing a computer system or such-like is disclosed that includes a hierarchy of field replaceable units (FRUs). Each FRU in the hierarchy has a...
US-6,973,398 System level reduction of clock skew based on local thermal profiling
A method and apparatus for adjusting clock skew involves sensing a temperature at a location on an integrated circuit. A temperature sensor indicates a...
US-6,973,391 Method for predicting whether a failure of an electrical device may occur
A method of predicting whether a failure of an electrical device may occur if a receiver within the electrical device is subjected to an electrical noise pulse....
US-6,973,078 Method and apparatus for implementing low latency crossbar switches with integrated storage signals
A digital crossbar switch utilizes an asynchronous RAM to provide high density and low latency storage and a write enable pulse generator to generate write...
US-6,972,605 High speed semi-dynamic flip-flop circuit
A high-speed semi-dynamic flip-flop circuit uses a keeper transistor to replace the back-to-back inverter keeper circuit of prior art semi-dynamic flip-flop...
US-6,972,596 Method and apparatus for amplifying capacitively coupled inter-chip communication signals
One embodiment of the present invention provides a system that amplifies capacitively coupled inter-chip communication signals. During operation, the system...
US-6,972,333 Preparation of quinacridonequinones and substituted derivatives of same
A process for by oxidizing a quinacridone in a liquid medium with a non-metal oxidant producing a quinacridonequinone.
US-6,971,097 Method and apparatus for implementing concurrently running jobs on an extended virtual machine using different...
Methods and apparatus for implementing a virtual machine that supports the execution of more than one application per virtual machine process are described....
US-6,971,096 Transaction data structure for process communications among network-distributed applications
A process automation application, referred to as a commerce exchange server, for sending transaction messages between application programs uses a transaction...
US-6,971,079 Accuracy of timing analysis using region-based voltage drop budgets
A method and apparatus for improving the timing accuracy of an integrated circuit through region-based voltage drop budgets is provided. Further, a method for...
US-6,971,048 Testing device driver hardening
A test mechanism for testing device driver hardening includes an intercept mechanism for intercepting device driver access calls from a device driver under test...
US-6,970,991 Computer system with virtual memory and paging mechanism
A computer system supports virtual memory and a paging mechanism. When a new process is created, this occupies one or more memory region. In one embodiment, at...
US-6,970,980 System with multicast invalidations and split ownership and access right coherence mechanism
Various systems and methods for using a directory based coherency protocol in a system that employs a split ownership and access right cache coherence mechanism...
US-6,970,979 System with virtual address networks and split ownership and access right coherence mechanism
A computer system may include a directory, several active devices configured to access data, an address network configured to convey address packets...
US-6,970,948 Configuring system units using on-board class information
A method of automatic configuration of field replaceable units in a system includes steps of accessing configuration management system (CMS) class information...
US-6,970,941 System and method for separating addresses from the delivery scheme in a virtual private network
Methods and systems consistent with the present invention establish a virtual network on top of current IP network naming schemes. The virtual network uses a...
US-6,970,898 System and method for forcing floating point status information to selected values
A floating point flag forcing circuit comprising an circuit and a result assembler. The circuit receives a plurality of floating point operands, analyzes the...
US-6,970,873 Configurable mechanism and abstract API model for directory operations
A computing device including a method of adding to a directory information tree involving the steps of accessing a template name, reading a template according to...
US-6,970,869 Method and apparatus to discover services and negotiate capabilities
A service discovery protocol may allow clients in a distributed computing environment to search for services. Service providers (or a listener agent) may respond...
US-6,970,862 Method and system for answering online certificate status protocol (OCSP) requests without certificate...
Methods and systems in accordance with the present invention efficiently validate digital certificates by answering Online Certificate Status Protocol ("OCSP")...
US-6,970,353 Fan holder and components cooling duct assembly
A computer component cooling apparatus is described. The cooling apparatus may include a fan assembly. The fan assembly may be coupled to a computer chassis. A...
US-6,970,034 Method and apparatus for reducing power consumption due to gate leakage during sleep mode
One embodiment of the present invention provides a system that achieves low gate leakage current in an integrated circuit during sleep mode. Upon entering sleep...
US-6,969,173 Spectacle frame with detachable arms
A spectacle frame includes a temple piece for attachment to a lens or fabricated upon a lens surround. An arm of the frame includes a spring bar extending from...
US-6,968,547 Dynamic trap table interposition for efficient collection of trap statistics
A system and method for monitoring the performance of a computer system by dynamically interposing an instrumented trap table. A base address of a trap table,...
US-6,968,535 Service mapping method of enterprise application modeling and development for multi-tier service environments
A method for modeling an enterprise application to be performed over multiple tiers in a distributed computer system. The method includes generating a model,...
US-6,968,429 Method and apparatus for controlling line eviction in a cache
One embodiment of the present invention provides a system for controlling cache line eviction. The system operates by first receiving a sequence of instructions...
US-6,968,379 Latency-reducing bandwidth-prioritization for network servers and clients
Communications bandwidth available to network servers and computers running client processes is allocated among connections available to those devices based on...
US-6,968,378 Method and apparatus for identifying processing units to a network using network addresses obtained from...
A processing unit is connectable to a communications network. The processing unit has a data carrier reader operable to read a network identity from a portable...
US-6,968,291 Using and generating finite state machines to monitor system status
Provided are a method, system, and program for monitoring a system including a plurality of subcomponents. An implementation of a plurality of subcomponent...
US-6,967,487 Distributed diode fault check
A method and apparatus for testing for latent faults in the isolation devices of a system including redundant power supplies which supply power to one or more...
US-D511,694 Clock
US-D511,673 Combination padlock with horizontal locking bar
US-6,965,985 Sign generation bypass path to aligner for reducing signed data load latency
A method for reducing signed load latency in a microprocessor has been developed. The method includes transferring a part of data to an aligner via a bypass, and...
US-6,965,951 Device centric discovery and configuration for fabric devices
A host may be coupled to a fabric network. Fabric devices attached to the fabric network may be visible to the host through one or more host adapter ports. The...
US-6,965,905 Lock-free, parallel remembered sets
A multi-threaded garbage collector operates in increments and maintains, for each of a plurality of car sections in which it has divided a portion of the heap, a...
US-6,965,648 Source synchronous link integrity validation
A system may perform interconnect BIST (IBIST) testing on source synchronous links. The system may perform, at normal operating frequency, a source synchronous...
US-6,965,641 Apparatus and method for scalable buffering in a digital video decoder
A method of assigning a buffer size in a video decoder includes the step of establishing a first buffer size for a scalable buffer. A video data stream is then...
US-6,965,571 Precise error reporting
A method is provided for the precise reporting of errors in a flow of successive messages. The method includes detecting a transmission error in a message and...
US-6,965,559 Method, system, and program for discovering devices communicating through a switch
Provided is a computer implemented method, system, and program for discovering a topology of a switch from an initiator device. The switch includes a plurality...
US-6,965,250 Reduced delay power fail-safe circuit
An improved power fail-safe has an effective maximum delay of two gate delays from an input operably powered by a first power supply to a first and a second...
US-6,965,151 Device including a resistive path to introduce an equivalent RC circuit
Structures for providing devices that include resistive paths specifically designed to provide a predetermined resistance between the bulk material of the device...
US-6,965,019 Mono-and bis-hydrazone pigments
Mono- and Bis-Azo/Hydrazone Pyrrole Pigments and Methods for preparing same.
US-6,964,524 Interconnecting device for a data processing system
A light guide for an interconnecting device. The light guide comprises a first section having a Fiber Channel connector disposed therein and a second section...
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