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Apparatus and method for dynamically verifying information in a
Use of a policy object for verification in a distributed system. A machine downloads a policy object containing a reference to code governing verification of...
Managing scene graph memory using data staging
A system and method that manages scene graphs by data staging is contemplated. Data staging entails selectively loading only the portions of the scene graph that...
System and method for validating processor performance and functionality
A method and system for accurately validating performance and functionality of a processor in a timely manner is provided. First, a program is executed on a high...
Switching sample buffer context in response to sample requests for
real-time sample filtering and video generation
A graphics system configured with a scheduling network, a sample buffer, a rendering engine and a filtering engine. The rendering engine is configured to...
Method and apparatus for automatic accessibility assessment
The present invention provides a method and apparatus for automatic accessibility assessment. One embodiment of the present invention automatically executes and...
Populating binary compatible resource-constrained devices with content
verified using API definitions
Remote incremental program verification may be achieved by receiving content verified by at least one content provider, installing the content on a...
ASIC logic BIST employing registers seeded with differing primitive
A method and apparatus for performing a built-in self-test ("BIST") on an integrated circuit device are disclosed. A BIST controller comprises a logic built-in...
Protection for memory modification tracking
A dirty memory is operable to store dirty indicators, each dirty indicator being settable to a given value indicative that a page of memory associated therewith...
Data storage array employing block verification information to invoke
A data storage array employing block verification information to invoke initialization procedures. In one embodiment, a data storage subsystem includes a...
Modified glitch latch for use with power saving dynamic register file
In the Retirement Payload Array (RPA) of a microprocessor, the signal "READ" is logically combined with the primary clock signal "CLK" in a control circuit of a...
A method and system for the smart prefetching of instructions is disclosed. The method includes computing an effective memory latency of a request for data and...
Method and apparatus for merging data graphs using data identity control
A method for merging a first object graph with a second object graph, including packaging the first object graph into an internal representation, wherein the...
Method and apparatus for customizing Java API implementations
A method and system is provided for customizing Java API implementations. A plurality of class files is obtained, wherein the class files are capable of being...
Mechanism for graphical test exclusion
Methods and systems for administratively qualifying and disqualifying test programs of a suite as excludable from performance by a client are disclosed in...
A server blade may comprise a processor. The server blade may additionally comprise a removable media interface device. The server blade can be configured as a...
System and method for accessing functionality of a backend system from an
A system and method for automatically creating information useable to access functionality of a backend computer system coupled to an application server. The...
Methods and apparatus for numeric constant value inlining in virtual
Improved frameworks for loading and execution of portable, platform independent programming instructions within a virtual machine are disclosed. The improved...
Method and apparatus for rewriting bytecodes to minimize runtime checks
Methods and apparatus for reducing the number of runtime checks performed during the execution of a virtual machine. According to one aspect of the present...
Rating apparatus and method for evaluating bugs
A method of rating a bug, including reporting the bug to a business entity by an interested party, entering information regarding the bug into a database,...
Software application test coverage analyzer
A method for analyzing test coverage of a software application is provided. The method includes profiling an executable of the software application to generate...
Low overhead snapshot in a storage array using a tree-of-slabs metadata
A method for creating a point-in-time copy of a data store. A command to create a point-in-time copy of an original data store is received. The processing of...
Method and system for facilitating relocation of devices on a network
Methods and systems consistent with the present invention provide a Supernet, a private network constructed out of components from a public-network...
Networked video projector apparatus and method of projecting a video frame
on a video projector
A video projector including a network adapter, a microprocessor physically and electrically coupled to the network adapter, a graphics adapter physically and...
Pulse shaper circuit for sense amplifier enable driver
A sense amplifier pulse shaping circuit maintains a relationship between a sense amplifier enable signal and a sense amplifier equalization enable signal while...
Methods and apparatus for efficiently accessing periodically broadcast data
The invention relates to methods and apparatus for accessing data that is periodically transmitted by a broadcaster. In accordance with one aspect of the...
Web-based enterprise management with multiple repository capability
A transport neutral technique allows an object manager to communicate with a CIM repository using any of a variety of protocols. The object manager software is...
Method and apparatus for fast, local CORBA object references
Methods and apparatus for reducing computing overhead by creating fast, local-only objects in a distributed client/server based computing system are disclosed....
Region-based voltage drop budgets for low-power design
A method and apparatus for assigning a set of region-based voltage drop budgets to an integrated circuit is provided. Further, a method for partitioning an...
Memory/Transmission medium failure handling controller and method
A memory controller may include a check bit encoder circuit and a check/correct circuit. The check bit encoder circuit is coupled to receive a data block to be...
Method and apparatus for predicting hot spots in cache memories
One embodiment of the present invention provides a system for predicting hot spots in a cache memory. Upon receiving a memory operation at the cache, the system...
Supporting non-hotswap 64-bit CPCI cards in a HA system
The present invention provides for systems and apparatus that support non-hotswappable (non-HA) 64-bit Compact Peripheral Component Interconnect (CPCI) cards so...
Mechanism for reconfiguring a server without incurring server down time
A mechanism for reconfiguring a server without incurring any server down time is disclosed. At startup time, a server constructs a set of configuration data...
Resource adapter and XML descriptor for use in a client server environment
utilizing an enterprise information...
A resource adapter for use in client server computer configurations utilizing enterprise information systems is disclosed. The file format defines the contract...
System and method for extracting the high part of a floating point operand
A method and system determine a high part of a floating point operand. Exponent field bits and fraction field bits of a result are set to a zero if the...
Method and apparatus solving problems having interval parameters
One embodiment of the present invention provides a system that solves a problem involving an interval parameter p through an interval solution process. During...
Low-complexity, high accuracy model of a CPU anti-resonance system
A low-complexity, high accuracy model of a CPU anti-resonance system has been developed. The model includes a simulated load model, a simulated transistor that...
Method and apparatus for facilitating use of a pre-shared secret key with
One embodiment of the present invention provides a system that facilitates a key exchange that operates with a pre-shared secret key and that hides identities of...
Switched network for low latency communication
A switched network includes a buffer-less switch coupling the sending nodes and the receiving nodes. The switch transmits packets successfully delivered to the...
System and method for providing software upgrades to a vehicle
An system and method for providing software upgrades to components of a vehicle, wherein the labor, time and expense of providing the upgrades are minimized. In...
Method for triggering flow control packets
A method triggers the transmission of a flow control packet between a receiving device and a sending device on the basis of space available to receive data in a...
Insertion and extraction mechanism for circuit boards
A mechanism for insertion of a circuit board into a rack assembly and extraction of a circuit board from the rack assembly. The mechanism may include a pair of...
Computing apparatus with cooling fan
Computing apparatus including a housing that defines a cavity. The computer apparatus further includes within the cavity multiple computing components, such as a...
Dynamically adjusting a number of rendering passes in a graphics system
A graphics system includes a hardware accelerator and a frame buffer. The frame buffer includes a sample storage area and a double-buffered display pixel area....
Method for reduction of possible renderable graphics primitive shapes for
A graphics system and method for rendering a plurality of triangles. Information regarding the triangle may first be received. The method may then determine the...
System, method and apparatus for improving sense amplifier performance
characteristics using process feedback
A system and method of adjusting a sense amplifier to compensate for the process-type of the sense amplifier includes determining a process-type of the sense...
Error detection/correction code which detects and corrects component
failure and which provides single bit...
A memory controller comprises a check bit encoder circuit and a check/correct circuit. The check bit encoder circuit is coupled to receive a data block to be...
Inexpensive secure on-line certification authority system and method
A certification authority generates certificates in response to respective certification requests. The certification authority generally includes a computer that...
Apparatus and method for dual access to a banked and pipelined data cache
In a data cache unit that exchanges data signal groups with at least two execution units, the operation of the data cache unit is implemented as a three-stage...