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Patent # Description
US-7,130,973 Method and apparatus to restore data redundancy and utilize spare storage spaces
Methods and apparatuses to restore data redundancy in a storage system with a storage virtualization engine. In one aspect of the invention, a method to restore...
US-7,130,957 Storage system structure for storing relational cache metadata
A storage system includes a cache and a collection of metadata, organized by their associations with regard to the data they represent. In one embodiment, the...
US-7,130,956 Storage system including hierarchical cache metadata
A storage system including hierarchical cache metadata storages includes a cache, a first metadata storage, and a second metadata storage. In one embodiment, the...
US-7,130,905 System and method for coordinating access to data for a distributed application
A system and method for controlling access to data in a distributed computer system. Distributed Token Manager (DTM) is a system-level service that coordinates...
US-7,130,898 Mechanism for facilitating invocation of a service
An application proxy is disclosed for shielding the complexities of invoking a service from a higher level mechanism, such as a process engine. The application...
US-7,130,881 Remote execution model for distributed application launch and control
An invention is provided for a remote execution system. The remote execution system includes a first application, such as a server application, having a first...
US-7,130,839 Method and system for grouping entries in a directory server by group memberships defined by roles
Role is a comprehensive grouping mechanism. In a client-server directory system, roles transfer some of the complexity to the directory server. A role is defined...
US-7,130,773 Method and apparatus for processing data using objects
One embodiment of the invention provides a method for processing actuator, sensor or radio frequency identification (RFID) tag data. The method includes...
US-7,130,340 Noise margin self-diagnostic receiver logic
A noise margin self-diagnostic receiver circuit has been developed. The self-diagnostic circuit includes one comparator for comparing the signal voltage to a...
US-7,129,941 Sample replication mode with depth value calculation
A system and method are disclosed for rendering polygons. Parameter values may be rendered for only one sample position of a plurality of neighboring sample...
US-7,129,851 Indicator feedback mechanism
An indicator assembly for a computer system can comprise a light guide for directing light from an indicator light source to an exterior panel of the computer...
US-7,129,818 Method and system for determining whether a person is potentially unavailable for communication
In a method for determining whether a person is potentially unavailable for communication, sensors are provided at a location to obtain information regarding a...
US-7,129,800 Compensation technique to mitigate aging effects in integrated circuit components
A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL)...
US-7,129,774 Method and apparatus for generating a reference signal
A method and apparatus for generating a reference signal involves (i) generating a CTAT voltage and a PTAT voltage, (ii) generating a first digital signal and a...
US-7,129,712 Attofarad capacitance measurement
An electrical circuit for determining a capacitance is described. The electrical circuit includes a first device, a rectifying circuit and a feedback circuit....
US-7,128,333 Collapsible golf cart
A golf bag cart (10) having a frame (14), a handle (22), first and second rear wheels (18, 20), and first and second wheel struts (52, 54), to which the first...
US-D531,062 Clock with oversized dial
US-D531,058 Clock with folding base
US-D531,057 Swiveling projection clock
US-D530,940 Eye wear display case
US-7,127,704 Interactive software engineering tool with support for embedded lexical contexts
In response to programmer input of a trigger token, a program editor creates a pair of boundary tokens encapsulating an embedded lexical context and positions an...
US-7,127,687 Method and apparatus for determining transistor sizes
A method of determining at least one ratio of transistor sizes. The method includes creating a sizing model by replacing at least one logic element in a circuit...
US-7,127,643 Method and apparatus for fixing bit errors encountered during cache references without blocking
One embodiment of the present invention provides a system that fixes bit errors encountered during references to a cache memory. During execution of an...
US-7,127,640 On-chip testing of embedded memories using Address Space Identifier bus in SPARC architectures
A system for on-chip testing of embedded memories using Address Space Identifier (ASI) bus in Scalable Processor ARChitecture (SPARC) microprocessors. An...
US-7,127,613 Secured peer-to-peer network data exchange
A system and method for providing secure exchange of messages between peers in peer groups. Embodiments may be used to provide secured sessions between peers in...
US-7,127,601 System and method for delivering FPGA programming
A system and method for facilitating delivery of instructions for operating a controller (e.g., an FPGA--Field Programmable Gate Array) of a hardware device...
US-7,127,592 Method and apparatus for dynamically allocating registers in a windowed architecture
One embodiment of the present invention provides a system that dynamically allocates physical registers in a windowed processor architecture. The system includes...
US-7,127,504 System and method of applying power laws in optimizing network traffic
A system and method of predicting network data traffic includes coupling a first group of clients to a current server that results in a current CPU utilization...
US-7,127,465 Memory-efficient metadata organization in a storage array
A metadata tree structure having a plurality of nodes (slabs), each node containing a MD table. Each of the MD tables has a plurality of entries. Each of the...
US-7,127,386 Java telematics emulator
A system for emulating a telematics client is provided. The system includes a workstation in communication with a display screen. A software stack configured to...
US-7,126,827 Electronics assembly
In some embodiments, an electronics assembly may include a frame with a motherboard and a plurality of daughterboards. The frame may have an opening opposite the...
US-7,125,764 Method of producing solid electrolytic capacitor
A manufacturing method according to the present invention of a solid electrolytic capacitor includes: a step of immersing a anode body on which the dielectrics...
US-7,124,887 Extension handle and golf bag with extension handle
Briefly, one preferred embodiment of the present invention (10) is an extension handle (26) for a golf bag (12) having a top opening (19), and carrying straps...
US-D530,735 Calculator
US-D530,541 Eye wear display case
US-7,124,407 Method and apparatus for caching native code in a virtual machine interpreter
Techniques for increasing the performance of virtual machines are disclosed. It can be determined whether a program instruction which is to be executed by the...
US-7,124,403 Methods and apparatus for managing defunct processes
The present invention relates to managing defunct processes. A parent process that does not collect exit information associated with a child process may leave a...
US-7,124,331 Method and apparatus for providing fault-tolerance for temporary results within a CPU
One embodiment of the present invention provides a system that corrects bit errors in temporary results within a central processing unit (CPU). During operation,...
US-7,124,328 Capturing system error messages
The present invention provides a method and apparatus for capturing system error messages. The method includes accessing information associated with an error....
US-7,124,321 Adaptive throttling
A computer system is provided having at least one processing resource, at least one power resource and at least one redundant power resource. The at least one...
US-7,124,319 Delay compensation for synchronous processing sets
A fault tolerant computing system is provided comprising two or more processing sets that operate in synchronism with one another. The two processing sets are...
US-7,124,295 Delta CRL enhancement
A method and apparatus for producing an enhanced CRL. In response to a request containing an identifier of the most recently owned CRL stored by the requested, a...
US-7,124,291 System and method for eliminating static initialization overhead by memory space cloning of a master runtime...
A system and method for eliminating static initialization overhead by memory space cloning of a master runtime system process is presented. A master runtime...
US-7,124,284 Method and apparatus for processing a complex instruction for execution and retirement
A method and apparatus to determine readiness of a complex instruction for retirement includes decoding a complex instruction into a plurality of helper...
US-7,124,254 Method and structure for monitoring pollution and prefetches due to speculative accesses
A method and structure for equipping a cache with information to enable the processor to track and report whether a given speculative access causes prefetches...
US-7,124,253 Supporting directory-based cache coherence in an object-addressed memory hierarchy
One embodiment of the present invention provides a system that supports directory-based cache coherence in an object-addressed memory hierarchy in a computer...
US-7,124,228 Bus communication architecture, in particular for multicomputing systems
A computer system comprises first and second computer boards, each having a processor, onboard memory, an onboard bus, e.g. a processor bus, and a bus-to-bus...
US-7,124,176 Discovering thin-client parameters in an enterprise network environment
A thin-client device broadcasts a configuration request message over a network. In response to the configuration request message, the thin-client device receives...
US-7,124,160 Processing architecture having parallel arithmetic capability
According to the invention, a processing core is disclosed that includes a first source register, a number of second operands, a destination register, and a...
US-7,123,995 Dynamic circuit operation adjustment based on distributed on-chip temperature sensors
A plurality of on-chip temperature sensors are selectively distributed across an integrated circuit. The temperature sensors generate signals indicative of...
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