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Patent # Description
US-5,557,581 Logic and memory circuit with reduced input-to-output signal propagation delay
A logic and memory circuit with reduced input-to-output signal propagation delay includes signal processor and memory elements connected in parallel for...
US-5,557,188 Smart battery system and interface
A battery system includes intelligence to allow the battery system to control various aspects of the charging and discharging of the battery, as well as to...
US-5,556,897 Primer solution compositions and method of forming adhesive layer on tooth surface
A primer solution composition to be applied to a tooth surface, which comprises (a) at least one metal compound selected from the group consisting of an iron...
US-D373,744 Hanging egg shaped bunny ornament
US-5,555,540 ASIC bus structure
A bi-directional ring bus structure is formed on an integrated circuit from a conductive bus and M X:1 multiplexer modules (where M is an integer .gtoreq.2),...
US-5,555,416 Automated software installation and operating environment configuration for a computer system based on...
A boot device, a local or remote install media, and a local or remote storage device are provided to a computer system. The boot device comprises an install...
US-5,555,401 Self configuring device system
A method and apparatus for automatically generating device names in a computer system, wherein device names are generated to reflect the physical realities of...
US-5,553,601 Barbecue
A barbecue adapted for portability and being gas-fired. A parallel smoker plate assembly intermediate a gas burner and a cooking plane enhances heat transfer to...
US-5,553,296 Touch screen power control in a computer system
A touch screen power control function in a computer system, wherein a touch screen input device is employed to control power modes for the computer system. A...
US-5,552,467 Vegetable oil based thermosetting lithographic ink system
Rapid thermosetting, low VOC web offset lithographic inks are prepared in the instant invention from solid resin, drying oil alkyds, bodied drying oil, vegetable...
US-5,551,585 Process for the surface treatment of lithographic printing plate precursors
A process is disclosed to produce a fine honeycomb grain with matte finishing on an aluminum surface in alkaline solution with or without electrical treatment....
US-5,551,000 I/O cache with dual tag arrays
An I/O streaming cache is provided to improve the data transfer bandwidth of an I/O bus of a computer system. The I/O streaming cache comprises at least one data...
US-5,550,976 Decentralized distributed asynchronous object oriented system and method for electronic data management,...
A highly secure, virus resistant, tamper resistant, object oriented, data processing system for depositing, withdrawing and communicating electronic data between...
US-5,550,960 Method and apparatus for performing dynamic texture mapping for complex surfaces
A system and process is provided which enables the dynamic mapping of texture to a variety of primitives, including complex primitives such as non-uniform...
US-5,550,301 Dried catalytic systems for decomposition of organic hydroperoxides
Organic hydroperoxides are decomposed by drying a reaction mixture containing the organic hydroperoxide and an organic solvent such that said dried reaction...
US-5,548,739 Method and apparatus for rapidly retrieving data from a physically addressed data storage structure using...
In a computer system having a number of page partitioned and virtually addressed address spaces, a physically addressed data storage structure and its...
US-5,548,646 System for signatureless transmission and reception of data packets between computer networks
A system for automatically encrypting and decrypting data packet sent from a source host to a destination host across a public internetwork. A tunnelling bridge...
US-5,548,620 Zero latency synchronized method and apparatus for system having at least two clock domains
A method and apparatus for implementing a zero latency synchronizer that permits the reliable transfer of data between clock domains by placing a metastability...
US-5,546,554 Apparatus for dynamic register management in a floating point unit
In a processor, an instruction unit that issues a plurality of instructions is coupled to a mapping unit. Each instruction contains at least one "virtual"...
US-5,546,277 Computer component torsional latching mechanism and method
The disclosure relates to a latching mechanism for securing an enclosure case of a computer system to a rack. The rack has two pairs of spaced apart posts, each...
US-5,546,274 Three-dimensional compact array of electronic circuitry
A three-dimensional compact array of electronic circuitry includes a plurality of stacked modular compact arrays of electronic circuitry. Each modular compact...
US-5,546,022 Static logic circuit with improved output signal levels
A static logic circuit with improved output signal levels includes a static complementary MOSFET circuit with a signal node and pull-up and pull-down amplifiers,...
US-5,545,325 Combined aerobic & anaerobic treating method & facility for hog wastewater
A combined aerobic and anaerobic treating method and facility for treating hog wastewater, in which, wastewater flows through six consecutive steps, namely: 1...
US-5,544,974 System for underground storage and delivery of liquid product, and recovery of leakage
A system for the storage and dispensing of liquid product from an underground installation comprises a storage tank which bears on its top a containment chamber...
US-5,544,969 Stacked enclosure locking mechanism
A module is sandwiched between an underlying member and a superimposed enclosure. The underlying member may be a base or another enclosure. The module is...
US-5,544,332 Method for preventing deadlock in a multi-bus computer system
Deadlock detection and masking systems are incorporated into a bus coupler intercoupling at least two buses, wherein at least one master is coupled to each bus...
US-5,544,306 Flexible dram access in a frame buffer memory and system
A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts...
US-5,543,824 Apparatus for selecting frame buffers for display in a double buffered display system
A double buffered output display system including a first frame buffer, a second frame buffer, a multiplexor for furnishing data to an output display from one of...
US-5,543,662 Low heat loss and secure chip carrier for cryogenic cooling
An integrated circuit package is disclosed. The integrated circuit package includes a substrate having a cavity formed therein for enclosing an integrated...
US-5,542,069 Method and apparatus for simulating input events in a windowed environment
An input device emulator comprises an interpreter and a router is provided to a windowed environment. The interpreter reads and interprets commands of a first...
US-5,541,547 Test generator system for controllably inducing power pin latch-up and signal pin latch-up in a CMOS device
A latch-up pulse generator system includes a latch-up pulse generator coupled to first and second power supplies, for outputting JEDEC-standardized first and...
US-5,541,536 Rubberband logic
A circuit for evaluating logic inputs responsive to a reference clock, which circuit includes a first clock terminal for coupling with a first clock, the first...
US-5,541,526 Sense amplifier having two intermediate voltage switching levels to increase speed
The multiple-input OR-gate includes a set of pull down transistors connected in parallel to a common signal line. A pair of first and second inverters are...
US-5,540,833 Sulfur tolerant bimetallic zeolitic reforming catalysts
New compositions of matter comprise a metal from the group consisting of platinum, rhodium and palladium, a metal from the first row of Group VIII of the...
US-5,540,548 Redundant blower unit
A redundant blower unit is installed in a rack above another unit containing heat-emitting electrical elements (such as CPU cards) in order to draw air through...
US-5,539,894 Method and apparatus for optimizing a sector cache tag, block and sub-block structure base on main memory size
A sector cache tag structure for a computer system with a cache memory and a maximum amount of system memory is disclosed. Upon initial power-up of the computer...
US-5,539,680 Method and apparatus for analyzing finite state machines
A computer system for generating a summary of test coverage for a hardware description. The hardware description corresponds to a finite state machine (FSM)....
US-5,539,430 Pipelined read write operations in a high speed frame buffer system
A frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, row addressing decoding apparatus and...
US-5,537,665 Multiple bank column redundancy intialization controller for cache RAM
An apparatus and method for controlling the initialization of shifting circuitry which provides column redundancy for multiple banks of cache memory on-board a...
US-5,537,145 Evaluation method and system for performance of flat panel displays and interface hardware
A system and method for testing and evaluating a display device and its associated display drive circuitry through computer generated graphic test patterns which...
US-5,536,685 Low heat loss and secure chip carrier for cryogenic cooling
An integrated circuit package is disclosed. The integrated circuit package includes a substrate having a cavity formed therein for enclosing an integrated...
US-5,535,451 Pants garment with buttocks enhancement
A pants garment of stretch material is formed of right and left rear panels and right and left front panels. Each of the panels includes a rise portion and a leg...
US-5,535,223 Method and apparatus for the verification and testing of electrical circuits
The system of the present invention provides for the verification and testing of electrical circuits and the generation of the information necessary to interface...
US-5,535,199 TCP/IP header compression X.25 networks
A process and apparatus are disclosed wherein a local data terminal equipment ("DTE" ) node which has the capability of using RFC 1144 TCP/IP header...
US-5,533,187 Multiple block mode operations in a frame buffer system designed for windowing operations
A frame buffer having a memory array, circuitry for accessing the array, a plurality of color value registers for storing a plurality of color values which may...
US-5,532,954 Single in-line memory module
A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions. A printed circuit board having a multiplicity of DRAM...
US-5,532,625 Wave propagation logic
A wave propagation circuit having one or more circuit stages. Each circuit stage preferably has the same number of evaluation devices as the number of logic...
US-5,532,560 Photosensitive automatic blind controller
There is disclosed a photosensitive automatic controller for use with window coverings in particular for use with venetian blinds. The controller includes a...
US-5,531,789 Sealing system of an artificial internal organ
An artificial internal organ, such as an artificial heart, comprising a pump unit through which blood circulates and a drive shaft for driving the pump unit, the...
US-5,531,442 Hockey puck with integral rollers and method of assembly
A hockey puck having integral rollers for use on hard surfaces other than ice. The rollers of the hockey puck, which are captured within and project from both...
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