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Patent # Description
US-5,539,430 Pipelined read write operations in a high speed frame buffer system
A frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, row addressing decoding apparatus and...
US-5,537,665 Multiple bank column redundancy intialization controller for cache RAM
An apparatus and method for controlling the initialization of shifting circuitry which provides column redundancy for multiple banks of cache memory on-board a...
US-5,537,145 Evaluation method and system for performance of flat panel displays and interface hardware
A system and method for testing and evaluating a display device and its associated display drive circuitry through computer generated graphic test patterns which...
US-5,536,685 Low heat loss and secure chip carrier for cryogenic cooling
An integrated circuit package is disclosed. The integrated circuit package includes a substrate having a cavity formed therein for enclosing an integrated...
US-5,535,451 Pants garment with buttocks enhancement
A pants garment of stretch material is formed of right and left rear panels and right and left front panels. Each of the panels includes a rise portion and a leg...
US-5,535,223 Method and apparatus for the verification and testing of electrical circuits
The system of the present invention provides for the verification and testing of electrical circuits and the generation of the information necessary to interface...
US-5,535,199 TCP/IP header compression X.25 networks
A process and apparatus are disclosed wherein a local data terminal equipment ("DTE" ) node which has the capability of using RFC 1144 TCP/IP header...
US-5,533,187 Multiple block mode operations in a frame buffer system designed for windowing operations
A frame buffer having a memory array, circuitry for accessing the array, a plurality of color value registers for storing a plurality of color values which may...
US-5,532,954 Single in-line memory module
A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions. A printed circuit board having a multiplicity of DRAM...
US-5,532,625 Wave propagation logic
A wave propagation circuit having one or more circuit stages. Each circuit stage preferably has the same number of evaluation devices as the number of logic...
US-5,532,560 Photosensitive automatic blind controller
There is disclosed a photosensitive automatic controller for use with window coverings in particular for use with venetian blinds. The controller includes a...
US-5,531,789 Sealing system of an artificial internal organ
An artificial internal organ, such as an artificial heart, comprising a pump unit through which blood circulates and a drive shaft for driving the pump unit, the...
US-5,531,442 Hockey puck with integral rollers and method of assembly
A hockey puck having integral rollers for use on hard surfaces other than ice. The rollers of the hockey puck, which are captured within and project from both...
US-5,530,878 Simplified power system with a single power converter providing low power consumption and a soft on/off feature
A computer power system with a keyboard, a computer housing, and a single AC to DC power converter that generates a DC power signal as long as it is energized by...
US-5,530,852 Method for extracting profiles and topics from a first file written in a first markup language and generating...
A computer-implemented method and system for of retrieving information. A first file of information is received which includes a first markup language to...
US-5,530,038 Primer composition and curable composition
A curable composition comprising a polymerizable monomer having an acidic group in its molecule and an initiator. The composition has a viscosity in the range of...
US-5,528,751 Frame buffer system designed for windowing operations
A frame buffer designed to be coupled to a data bus and to an output display in a computer system, the frame buffer including an array of memory cells for...
US-5,528,638 Multiple phase shifted clocks generation using a minimal set of signals from a PLL
An inventive apparatus for generating a plurality of phase-shifted clocks on an IC, including a PLL disposed at a first location for generating a reference clock...
US-5,528,165 Logic signal validity verification apparatus
A logic signal validity verifier for use in determining the validity of the logic states of a group of logic signals includes an inactive signal fault monitor...
US-5,528,083 Thin film chip capacitor for electrical noise reduction in integrated circuits
An integrated circuit chip and flat capacitor assembly are connected with short bonding wires to reduce electrical noise. A flat chip capacitor is coupled to the...
US-D370,686 Grip-head handle
US-5,524,195 Graphical user interface for interactive television with an animated agent
A graphical user interface for displaying and selecting video programs, such as video on demand, includes a video on demand server coupled to a communication...
US-5,521,874 High speed differential to single ended sense amplifier
A differential to single ended sense amplifier utilizes a minimum number of stages to convert a differential input signal received from complementary bit lines...
US-5,520,236 Greenhouse curtain system
A novel greenhouse curtain system has a plurality of movable curtains oriented vertically one above the other to form a flexible wall. Each curtain is supported...
US-5,520,217 Directional valve
A solenoid operated directional valve including a main section having a reciprocally mounted main fluid controlling valving member moveable between three...
US-5,519,851 Portable PCMCIA interface for a host computer
A portable PCMCIA interface for a host computer having a system bus. In one embodiment, the host computer is a SPARC based computer having an SBus and running...
US-5,519,825 Method and apparatus for NTSC display of full range animation
Full-motion animation video is displayed in a computer system through use of sprite objects. The sprite objects define the images on the output display, and the...
US-5,519,715 Full-speed microprocessor testing employing boundary scan
A method is disclosed for loading a compiled test program into a microprocessor's internal caches and then controlling the execution of that program. Initially,...
US-5,517,611 Floating-point processor for a high performance three dimensional graphics accelerator
A floating-point processor implements specialized graphics micro instructions. The specialized graphics micro instructions include a swap micro instruction which...
US-5,517,133 Multiple-input OR-gate employing a sense amplifier
The multiple-input OR-gate includes a set of pull down transistors connected in parallel to a common signal line. A pair of first and second inverters are...
US-5,517,130 Method and structure for reducing noise in output buffer circuits
A method and structure for controlling ground bounce and power supply noise during switching is provided in which a plurality of pull-up and/or pull-down...
US-5,516,964 Hydrocarbon isomerization using solid superacid catalysts comprising platinum metal
An isomerization process is provided which process utilizes a sulfated solid catalyst comprising (1) oxide or hydroxide of Group III or Group IV element, e.g....
US-5,515,538 Apparatus and method for interrupt handling in a multi-threaded operating system kernel
The disclosed invention is a method and apparatus for use in handling interrupts in a data processing system where the kernel is preemptible, has real-time...
US-5,515,509 Method and apparatus for implementing self-organization in a wireless local area network
A method and apparatus for implementing self-organization in a wireless local area network ("LAN"). Each LAN is divided into a plurality of cells. Each cell is...
US-5,513,360 Computer microphone powered by internal battery or computer hardware
A computer microphone with a dual power source capability is disclosed. This dual power source capability allows the microphone to receive power from an internal...
US-5,513,192 Fault tolerant disk drive system with error detection and correction
A fault tolerant, magnetic disk drive array with error detection and correction. The present invention performs vertical parity checks and one or two additional...
US-5,513,186 Method and apparatus for interconnect testing without speed degradation
A method and apparatus is disclosed for advantageously implementing a full boundary scan test of input and bi-directional paths of an integrated circuit. The...
US-5,512,918 High speed method and apparatus for generating animation by means of a three-region frame buffer and associated...
A method and apparatus for quickly copying a first frame region into a second frame region. A video memory array comprising a plurality of video random access...
US-5,512,780 Inorganic chip-to-package interconnection circuit
An inorganic chip-to-package interconnection circuit is described. The circuit has a set of electrical conductors that are held together by a set of insulating...
US-5,512,420 Waterless presensitized plate comprising four layers
A camera speed lithographic plate precursor composition is used for the preparation of waterless, imaged printing plates. The plates comprise a solid substrate...
US-5,510,733 High speed circuit with CMOS and bipolar logic stages
An integrated circuit includes a bipolar logic stage and a CMOS logic stage. The bipolar logic stage includes a common emitter line positioned along a central...
US-5,510,732 Synchronizer circuit and method for reducing the occurrence of metastability conditions in digital systems
A digital system including a synchronizer circuit which significantly reduces the occurrence of metastability conditions during data transfer between a first...
US-5,510,558 Oxidative dehydrogenation of hydrocarbons with active carbon catalyst
Oxidative dehydrogenation of alkanes and alkylaromatic hydrocarbons is achieved by contact with an active carbon catalyst. In various aspects of the invention,...
US-5,509,130 Method and apparatus for grouping multiple instructions, issuing grouped instructions simultaneously, and...
In a pipelined processor, an instruction queue and an instruction control unit is provided to group and issue m instructions simultaneously per clock cycle for...
US-5,506,969 Method and apparatus for bus bandwidth management
A computer system includes bus bandwidth management for operation of a high-speed bus. The high-speed bus is coupled to a plurality of modules. A plurality of...
US-5,504,855 Method and apparatus for providing fast multi-color storage in a frame buffer
A frame buffer for accelerating the display of graphics data on an output display device which frame buffer includes a pair of color value registers each of...
US-5,504,700 Method and apparatus for high density sixteen and thirty-two megabyte single in-line memory module
The invention provides a method and apparatus for a memory device interface between a memory device and a CPU as well as the dimensions of the memory device. An...
US-5,503,472 Method and apparatus for assembly of a multi-disk pack unit
An apparatus and method are disclosed for minimizing the space required for a disk drive housing by mounting a disk drive unit in an enclosure of minimum size,...
US-5,502,837 Method and apparatus for clocking variable pixel frequencies and pixel depths in a memory display interface
A method and apparatus for synchronizing pixel data flow within a memory display interface (MDI) to enable variable pixel depths, and to support display devices...
US-5,502,211 Substituted dipyrromethanes and their preparation
New chemical compounds, bis(pyrrol-2-yl)halocarbylmethanes, also known as meso-halocarbyl dipyrromethanes, are made by recting pyrrole in either of two reaction...
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