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Method and apparatus for analyzing finite state machines
A computer system for generating a summary of test coverage for a hardware description. The hardware description corresponds to a finite state machine (FSM)....
Pipelined read write operations in a high speed frame buffer system
A frame buffer including an array of memory cells for storing data indicating pixels to be displayed on the output display, row addressing decoding apparatus and...
Multiple bank column redundancy intialization controller for cache RAM
An apparatus and method for controlling the initialization of shifting circuitry which provides column redundancy for multiple banks of cache memory on-board a...
Evaluation method and system for performance of flat panel displays and
A system and method for testing and evaluating a display device and its associated display drive circuitry through computer generated graphic test patterns which...
Low heat loss and secure chip carrier for cryogenic cooling
An integrated circuit package is disclosed. The integrated circuit package includes a substrate having a cavity formed therein for enclosing an integrated...
Pants garment with buttocks enhancement
A pants garment of stretch material is formed of right and left rear panels and right and left front panels. Each of the panels includes a rise portion and a leg...
Method and apparatus for the verification and testing of electrical
The system of the present invention provides for the verification and testing of electrical circuits and the generation of the information necessary to interface...
TCP/IP header compression X.25 networks
A process and apparatus are disclosed wherein a local data terminal equipment ("DTE" ) node which has the capability of using RFC 1144 TCP/IP header...
Multiple block mode operations in a frame buffer system designed for
A frame buffer having a memory array, circuitry for accessing the array, a plurality of color value registers for storing a plurality of color values which may...
Single in-line memory module
A full width single in-line memory module (SIMM) for dynamic random access memory (DRAM) memory expansions. A printed circuit board having a multiplicity of DRAM...
Wave propagation logic
A wave propagation circuit having one or more circuit stages. Each circuit stage preferably has the same number of evaluation devices as the number of logic...
Photosensitive automatic blind controller
There is disclosed a photosensitive automatic controller for use with window coverings in particular for use with venetian blinds. The controller includes a...
Sealing system of an artificial internal organ
An artificial internal organ, such as an artificial heart, comprising a pump unit through which blood circulates and a drive shaft for driving the pump unit, the...
Hockey puck with integral rollers and method of assembly
A hockey puck having integral rollers for use on hard surfaces other than ice. The rollers of the hockey puck, which are captured within and project from both...
Simplified power system with a single power converter providing low
power consumption and a soft on/off feature
A computer power system with a keyboard, a computer housing, and a single AC to DC power converter that generates a DC power signal as long as it is energized by...
Method for extracting profiles and topics from a first file written in a
first markup language and generating...
A computer-implemented method and system for of retrieving information. A first file of information is received which includes a first markup language to...
Primer composition and curable composition
A curable composition comprising a polymerizable monomer having an acidic group in its molecule and an initiator. The composition has a viscosity in the range of...
Frame buffer system designed for windowing operations
A frame buffer designed to be coupled to a data bus and to an output display in a computer system, the frame buffer including an array of memory cells for...
Multiple phase shifted clocks generation using a minimal set of signals
from a PLL
An inventive apparatus for generating a plurality of phase-shifted clocks on an IC, including a PLL disposed at a first location for generating a reference clock...
Logic signal validity verification apparatus
A logic signal validity verifier for use in determining the validity of the logic states of a group of logic signals includes an inactive signal fault monitor...
Thin film chip capacitor for electrical noise reduction in integrated
An integrated circuit chip and flat capacitor assembly are connected with short bonding wires to reduce electrical noise. A flat chip capacitor is coupled to the...
Graphical user interface for interactive television with an animated
A graphical user interface for displaying and selecting video programs, such as video on demand, includes a video on demand server coupled to a communication...
High speed differential to single ended sense amplifier
A differential to single ended sense amplifier utilizes a minimum number of stages to convert a differential input signal received from complementary bit lines...
Greenhouse curtain system
A novel greenhouse curtain system has a plurality of movable curtains oriented vertically one above the other to form a flexible wall. Each curtain is supported...
A solenoid operated directional valve including a main section having a reciprocally mounted main fluid controlling valving member moveable between three...
Portable PCMCIA interface for a host computer
A portable PCMCIA interface for a host computer having a system bus. In one embodiment, the host computer is a SPARC based computer having an SBus and running...
Method and apparatus for NTSC display of full range animation
Full-motion animation video is displayed in a computer system through use of sprite objects. The sprite objects define the images on the output display, and the...
Full-speed microprocessor testing employing boundary scan
A method is disclosed for loading a compiled test program into a microprocessor's internal caches and then controlling the execution of that program. Initially,...
Floating-point processor for a high performance three dimensional
A floating-point processor implements specialized graphics micro instructions. The specialized graphics micro instructions include a swap micro instruction which...
Multiple-input OR-gate employing a sense amplifier
The multiple-input OR-gate includes a set of pull down transistors connected in parallel to a common signal line. A pair of first and second inverters are...
Method and structure for reducing noise in output buffer circuits
A method and structure for controlling ground bounce and power supply noise during switching is provided in which a plurality of pull-up and/or pull-down...
Hydrocarbon isomerization using solid superacid catalysts comprising
An isomerization process is provided which process utilizes a sulfated solid catalyst comprising (1) oxide or hydroxide of Group III or Group IV element, e.g....
Apparatus and method for interrupt handling in a multi-threaded
operating system kernel
The disclosed invention is a method and apparatus for use in handling interrupts in a data processing system where the kernel is preemptible, has real-time...
Method and apparatus for implementing self-organization in a wireless
local area network
A method and apparatus for implementing self-organization in a wireless local area network ("LAN"). Each LAN is divided into a plurality of cells. Each cell is...
Computer microphone powered by internal battery or computer hardware
A computer microphone with a dual power source capability is disclosed. This dual power source capability allows the microphone to receive power from an internal...
Fault tolerant disk drive system with error detection and correction
A fault tolerant, magnetic disk drive array with error detection and correction. The present invention performs vertical parity checks and one or two additional...
Method and apparatus for interconnect testing without speed degradation
A method and apparatus is disclosed for advantageously implementing a full boundary scan test of input and bi-directional paths of an integrated circuit. The...
High speed method and apparatus for generating animation by means of a
three-region frame buffer and associated...
A method and apparatus for quickly copying a first frame region into a second frame region. A video memory array comprising a plurality of video random access...
Inorganic chip-to-package interconnection circuit
An inorganic chip-to-package interconnection circuit is described. The circuit has a set of electrical conductors that are held together by a set of insulating...
Waterless presensitized plate comprising four layers
A camera speed lithographic plate precursor composition is used for the preparation of waterless, imaged printing plates. The plates comprise a solid substrate...
High speed circuit with CMOS and bipolar logic stages
An integrated circuit includes a bipolar logic stage and a CMOS logic stage. The bipolar logic stage includes a common emitter line positioned along a central...
Synchronizer circuit and method for reducing the occurrence of
metastability conditions in digital systems
A digital system including a synchronizer circuit which significantly reduces the occurrence of metastability conditions during data transfer between a first...
Oxidative dehydrogenation of hydrocarbons with active carbon catalyst
Oxidative dehydrogenation of alkanes and alkylaromatic hydrocarbons is achieved by contact with an active carbon catalyst. In various aspects of the invention,...
Method and apparatus for grouping multiple instructions, issuing grouped
instructions simultaneously, and...
In a pipelined processor, an instruction queue and an instruction control unit is provided to group and issue m instructions simultaneously per clock cycle for...
Method and apparatus for bus bandwidth management
A computer system includes bus bandwidth management for operation of a high-speed bus. The high-speed bus is coupled to a plurality of modules. A plurality of...
Method and apparatus for providing fast multi-color storage in a frame
A frame buffer for accelerating the display of graphics data on an output display device which frame buffer includes a pair of color value registers each of...
Method and apparatus for high density sixteen and thirty-two megabyte
single in-line memory module
The invention provides a method and apparatus for a memory device interface between a memory device and a CPU as well as the dimensions of the memory device. An...
Method and apparatus for assembly of a multi-disk pack unit
An apparatus and method are disclosed for minimizing the space required for a disk drive housing by mounting a disk drive unit in an enclosure of minimum size,...
Method and apparatus for clocking variable pixel frequencies and pixel
depths in a memory display interface
A method and apparatus for synchronizing pixel data flow within a memory display interface (MDI) to enable variable pixel depths, and to support display devices...