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Patent # Description
US-5,602,795 Method and apparatus for implementing a high-speed dynamic line driver
A high speed line driver circuit that drives an output line based on an input line is disclosed. The high speed line driver circuit uses dynamic precharging of...
US-5,602,769 Method and apparatus for partially supporting subnormal operands in floating point multiplication
A method for fully supporting floating point multiplication using a combination of partial hardware support and partial software support traps to software when a...
US-D377,913 Slip-on wrist case for capsule components such as compasses or thermometers
US-5,600,848 Counterflow pipeline processor with instructions flowing in a first direction and instruction results flowing...
A general purpose computer capable of executing instructions of the type commonly found in multiple-address register-oriented instruction sets such as the SPARC...
US-5,600,650 Method and apparatus for synthesizing clock signals for use with an asynchronous transfer mode system having...
An asynchronous transfer mode (ATM) segmentation and reassembly (SAR) chip is provided for interfacing a host computer with an ATM system having a physical layer...
US-5,600,272 Digital damping method and apparatus for phase-locked loops
A damping circuit is described which includes a phase-and-frequency detector, a charge pump, a voltage-current oscillator and a capacitor. The ...
US-5,599,948 Substituted dipyrromethanes and their preparation
New chemical compounds, bis(pyrrol-2-yl)halocarbylmethanes, also known as meso-halocarbyl dipyrromethanes, are made by recting pyrrole in either of two reaction...
US-D377,761 Housing for capsule components such as thermometers, clocks or compasses
US-5,598,348 Method and apparatus for analyzing the power network of a VLSI circuit
A method and apparatus to model the power network of a VLSI circuit is described. The method includes the step of extracting the power network associated with a...
US-5,598,035 Integrated circuit package with external storage capacitor for improved signal quality for sensitive integrated...
A package for an integrated circuit is described. The package houses an integrated circuit with a signal quality sensitive integrated circuit element, such as a...
US-5,596,293 Noise resistant reset circuit for a phase detector in a phase-locked loop
A reset circuit for a phase detector in a phase-locked loop is described. A first set of input lines receives a first set of latched signals corresponding to a...
US-5,594,864 Method and apparatus for unobtrusively monitoring processor states and characterizing bottlenecks in a...
Methods and apparatus are presented for unobtrusively monitoring processor states and characterizing bottlenecks in an arbitrary customer workload. An...
US-5,594,846 Perspective correction of texture in graphics by adaptive approximation
A computer graphics system includes a texel value generator capably of generating texel values using a minimal amount of computationally intensive divisions...
US-5,592,679 Apparatus and method for distributed control in a processor architecture
The present invention provides a multi-level instruction scheduling system for controlling multiple execution pipes of a distributed data flow (DDF) processor....
US-5,592,370 Regulated complementary charge pump circuit
A charge pump circuit contains a first switch pass gate, a second switch pass gate, a high node regulator, and a low node regulator. The first switch pass gate...
US-5,592,103 System for fast switching of time critical input signals
A technique is provided for switching circuitry in a manner which allows the circuit to respond quickly to changes in some critical input signals expected to...
US-D377,125 Elbow rest
US-5,590,413 Radio transceiver having shared modulation and demodulation mixer circuits
A radio transceiver including an antenna for transmitting and receiving radio signals, a reception section for selecting a received carrier signal, a...
US-5,590,331 Method and apparatus for generating platform-standard object files containing machine-independent code
A method and apparatus for generating a platform-standard object file containing machine-independent abstract code. Source code which defines a procedure is...
US-5,590,286 Method and apparatus for the pipelining of data during direct memory accesses
A method and apparatus for the pipelining of data during direct memory accesses. The processor includes an external bus controller, which receives data...
US-5,589,323 Chemically stable ascorbate-based photographic developer and imaging process
The invention comprises a process for forming a high contrast photographic image including the steps of imagaewise exposing a silver halide photographic element...
US-5,588,131 System and method for a snooping and snarfing cache in a multiprocessor computer system
An improved multiprocessor computer system with an improved snarfing cache is disclosed. The multiprocessor system includes a main memory, I/O interface, and a...
US-5,588,114 Method and apparatus for passive loopback testing of software-controllable parallel ports
The present invention includes a connector that mates to the software-controllable parallel port output connector on a host device, a passive logic unit, and,...
US-5,588,060 Method and apparatus for a key-management scheme for internet protocols
A first data processing device (node I) is coupled to a private network which is in turn coupled to the Internet. A second data processing device (node J) is...
US-5,587,879 Mounting arrangement for computer hardware components and method
The disclosed invention relates to a computer system, including a crib device and chassis for installing and removing a hard drive to and from the chassis of the...
US-5,587,726 Method and apparatus for increasing the speed of operation of a double buffered display system
An output display system including an output display; apparatus for controlling the writing of information to the output display; and a double buffered memory...
US-5,587,709 High speed serial link for fully duplexed data communication
A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into...
US-5,587,406 Primer composition and curable composition
A curable composition comprising a polymerizable monomer having an acidic group in its molecule and an initiator. The composition has a viscosity in the range of...
US-5,586,283 Method and apparatus for the reduction of tablewalk latencies in a translation look aside buffer
A translation look aside buffer including virtual page table pointer tags provides a system and method for accessing page table entries in page memory of the...
US-5,584,014 Apparatus and method to preserve data in a set associative memory device
An apparatus and method to dynamically partition a set-associative memory device is described. The apparatus includes a set identification device to specify a...
US-5,583,821 Storage cell using low powered/low threshold CMOS pass transistors having reduced charge leakage
A storage cell includes a first bit line, a storage circuit, and a pass transistor. The storage circuit has a first storage node for holding a logic state...
US-5,581,761 Methods and apparatus for providing an extensible set of auxiliary services for objects in an object-oriented...
An extensible set of auxiliary services for objects in an object-oriented system. Every object in an object-oriented system is implemented by an associated...
US-5,581,729 Parallelized coherent read and writeback transaction processing system for use in a packet switched cache...
A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module,...
US-5,581,697 Method and apparatus for run-time error checking using dynamic patching
The invention provides a method and apparatus for dynamic patching for run-time error checking. With the present invention, a program to be error checked is read...
US-5,581,500 Memory cell with power supply induced reversed-bias pass transistors for reducing off-leakage current
A memory cell is disclosed. The memory cell operating within a power supply range that induces the pass transistor(s) of the memory cell to be reversed biased...
US-5,581,473 Method and apparatus for managing timing requirement specifications and confirmations and generating timing...
A repository, a loader, a model generator, a constraint generator, and a number of timing analysis tools, are provided for managing timing requirement...
US-5,579,480 System and method for traversing ATM networks based on forward and reverse virtual connection labels
In a communication network having a set of hosts and switch based label swapping communication nodes, each node has a control processor that is also a host that...
US-5,579,473 Interface controller for frame buffer random access memory devices
A frame buffer memory device controller that schedules and dispatches operations to frame buffer memory devices is disclosed. The frame buffer memory device...
US-5,579,212 Protective cover for a silicon chip device and method relating thereto
There is disclosed a cover for protecting the leads extending between a silicon chip device and an associated printed circuit board and their electrical...
US-5,577,252 Methods and apparatus for implementing secure name servers in an object-oriented system
A secure naming model for objects in an object-oriented system, wherein names are bound to objects within context objects. The context objects are implemented by...
US-5,577,251 Object oriented system for executing application call by using plurality of client-side subcontract mechanism...
The present invention provides an elegant and simple way to provide mechanisms for invocation of objects by client applications and for argument passing between...
US-5,577,232 Method and apparatus for allowing computer circuitry to function with updated versions of computer software
An arrangement for assuring the compatibility of versions of software produced for a particular computer hardware architecture including a hardware version...
US-5,577,001 High speed differential to single ended sense amplifier
A differential to single ended sense amplifier utilizes a minimum number of stages to convert a differential input signal received from complementary bit lines...
US-5,575,843 Process for improving color value of a pigment
A process for improving the color value of a pigment and for imparting stability to a water-based printing ink containing such pigment which comprises adding a...
US-5,572,734 Method and apparatus for locking arbitration on a remote bus
A master bus interconnecting multiple masters is coupled via any number of intervening buses to a slave bus interconnecting multiple slaves and masters. A lock...
US-5,572,729 Method for stateless rename propagation between hierarchical file name spaces
A method for the stateless propagation of rename's between hierarchial file name spaces is provided. Under the method any standard rename command may be used on...
US-5,572,690 Cascaded multistage counterflow pipeline processor for carrying distinct data in two opposite directions
A counterflow computing pipeline including a series of similar stages is disclosed. In the basic form of the pipeline, the stages are arranged in a linear...
US-5,572,666 System and method for generating pseudo-random instructions for design verification
A pseudo-random test system which generates the text for a sequence of assembly language instructions by intermixing text instructions generated by...
US-5,571,908 Porphyrins
The invention comprises new compositions of matter, which are iron, manganese, cobalt or ruthenium complexes of porphyrins having hydrogen, haloalkyl or haloaryl...
US-5,570,984 1/4 turn fastener
A combination of a plastic part and metal part functions as a fastener to attach a panel to the flange of a portion of a chassis for electronic equipment or the...
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