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Patent # Description
US-7,689,958 Partitioning for a massively parallel simulation system
A method involves building an intermediate form data flow graph (IFgraph) from an intermediate form data flow tree (IFtree) associated with the logic design,...
US-7,689,877 Method and system using checksums to repair data
A method for reconstructing corrupted data, which includes determining a number of non-parity disks (n), selecting a first combination of n-1 non-parity disks,...
US-7,689,813 Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor
Embodiments of the present invention provide a system that facilitates executing a memory barrier (membar) instruction in an execute-ahead processor, wherein the...
US-7,689,788 System and method for executing transactions
A method for executing transactions including obtaining a memory location required by a first transaction, where the first transaction is identified using a...
US-7,689,773 Methods and apparatus for estimating fair cache miss rates on a chip multiprocessor
A caching estimator process identifies a thread for determining the fair cache miss rate of the thread. The caching estimator process executes the thread...
US-7,689,751 PCI-express system
A method and system to facilitate Peripheral Component Interconnect Express (PCIe). The PCIe may be facilitated in such as way as to limit pins consumed by a...
US-7,689,723 Virtual cloned device node
A system and method for virtualizing a hardware device node for a network interface circuit or other device. In a clone driver's configuration file, multiple...
US-7,689,714 Load balancing computations in a multiprocessor system
A system and method for load-balancing routing of a computation within a multiprocessor system. The computation includes multiple branches of execution, not just...
US-7,689,702 Methods and apparatus for coordinating processing of network connections between two network protocol stacks
Methods and apparatus for processing a network connection are disclosed. The network connection is established by a first network protocol stack. A determination...
US-7,689,642 Efficient accuracy check for Newton-Raphson divide and square-root operations
One embodiment of the present invention provides a system that efficiently performs an accuracy-check computation for Newton-Raphson divide and square-root...
US-7,689,566 Method for defining non-native operating environments
Methods and systems for defining the partitioning between operating system environments are provided. In this method, network resources, devices, and...
US-7,689,399 Automatic extraction of design properties
A method for automatic extraction of design properties of a hardware design, is provided. The method includes running a hardware design simulation to generate...
US-7,688,455 Multi position detecting method and area detecting method in infrared rays type touch screen
A method for detecting the coordinates of multiple touching objects on an infrared touch screen, embodied on an apparatus, includes measuring and storing the...
US-7,687,772 Mass spectrometric imaging method under ambient conditions using electrospray-assisted laser desorption...
A mass spectrometric imaging method includes the steps of: forcing sequentially generated charge-laden liquid drops to move towards a receiving unit of a mass...
US-7,686,893 Washer for tanks
A tank washer comprising a housing which supports reciprocating spray nozzles for spaying the walls of a tank which is to be cleaned with a cleaning liquid. The...
US-7,686,064 Motorized/manual clutch of curtain track
A motorized and manual clutch of curtain track, set on a curtain track, the curtain track is provided with a belt which is driven by motor and carrier hook parts...
US-7,685,851 Security padlock having a secondary locking system
By providing a padlock having a primary shackle and a secondary shackle which is easily employed whenever the primary shackle has been cut, an effective, easily...
US-7,685,597 System and method for management of characterized resources
Providing a resource domain structure allows flexible management of resources. With flexible management, computations, such as threads and processes, do not have...
US-7,685,583 Obstruction-free mechanism for atomic update of multiple non-contiguous locations in shared memory
We present a technique for implementing obstruction-free atomic multi-target transactions that target special "transactionable" locations in shared memory. A...
US-7,685,580 Method and apparatus for selectively eliminating write barriers in snapshot-at-the beginning concurrent-marking...
In a computer system that uses a "snapshot-at-the-beginning" garbage collector and in which write barrier code is generated for pointer write instructions in...
US-7,685,575 Method and apparatus for analyzing an application
A method for analyzing an application involving obtaining a thread dump of a plurality of threads executing the application, analyzing the thread dump to obtain...
US-7,685,573 Flexible error trace mechanism
For a flexible error trace mechanism, embodiments may be implemented for C/C++ interface libraries, or in programs written in C/C++ or other programming...
US-7,685,572 Method of static analysis for race condition detection
A method for detecting a race condition using static analysis that includes determining a first permit set and a second permit set, and performing a static...
US-7,685,511 Framework for providing and using schema data for markup languages
Techniques for providing and using schema data for markup languages are disclosed. A schema model can be used to generate signed (or verifiable) schema data...
US-7,685,430 Initial password security accentuated by triple encryption and hashed cache table management on the hosted...
A method for remote services authentication in an internet hosted environment includes a high level process and functionality for a secure, practical and...
US-7,685,391 Kernel/user stack relocation during system uptime
Kernel and user stack data is stored in relocatable memory. A kernel thread or a user thread can move its own stack data by creating a relocation request and...
US-7,685,354 Multiple-core processor with flexible mapping of processor cores to cache banks
A multiple-core processor providing flexible mapping of processor cores to cache banks. In one embodiment, a processor may include a cache including a number of...
US-7,685,312 Resource location by address space allocation
A method for locating a free resource involves maintaining an address space containing a plurality of regions, wherein each of the plurality of regions is mapped...
US-7,685,309 System and method for separating addresses from the delivery scheme in a virtual private network
Methods and systems consistent with the present invention establish a virtual network on top of current IP network naming schemes. The virtual network uses a...
US-7,685,257 Portable thin client for the enterprise workspace
A system and method is provided for designing (or re-architecting) a personal digital assistant (PDA) as a portable thin client of a network. The portable thin...
US-7,685,253 System and method for disconnected operation of thin-client applications
System and method for disconnected operation of thin-client applications. In embodiments, a thin client on a client system may be used to access an application...
US-7,685,226 Mechanism for data migration across networks
In one embodiment, a method and apparatus for a mechanism for data migration across networks is disclosed. The method includes: randomly selecting a template...
US-7,684,563 Apparatus and method for implementing a unified hash algorithm pipeline
An apparatus and method for implementing a unified hash algorithm pipeline. In one embodiment, a cryptographic unit may include hash logic configured to compute...
US-7,684,423 System and method for virtual network interface cards based on internet protocol addresses
A system including a network interface card (NIC) associated with a Media Access Control (MAC) address and a host operatively connected to the NIC. The NIC...
US-7,684,394 System and method for increasing host visibility in network address translation environments
A mechanism for dynamically performing Network Address Translation that allows external devices to contact internal host systems that would otherwise be hidden...
US-7,684,267 Method and apparatus for memory redundancy in a microprocessor
An apparatus for redundancy of a memory array includes a primary memory array including a plurality of memory cells, one or more of which are defective. A...
US-7,684,191 Self-retaining vibration isolating fan mount assembly
A fan assembly for an electronic device is provided. The assembly comprises a fan housing, at least one bracket member, and at least one retention peg. The fan...
US-D612,302 Upper tray for baby walker
US-7,681,247 Anti-theft system and method for semiconductor devices and other electronic components
A semiconductor device includes a stored device identifier that is accessible to external systems, and a stored secret key that is inaccessible to external...
US-7,681,197 Nested monitor handling processes
A method of managing nested monitor locks in a computer program is provided for an application having at least a first thread and a second thread wherein a...
US-7,681,188 Locked prefetch scheduling in general cyclic regions
One embodiment of the present invention provides a system that facilitates locked prefetch scheduling in general cyclic regions of a computer program. The system...
US-7,681,019 Executing functions determined via a collection of operations from translated instructions
Reference architecture instructions are translated into target architecture operations. In some embodiments, an execution unit of a processor executes a function...
US-7,680,989 Instruction set architecture employing conditional multistore synchronization
We propose a class of mechanisms to support a new style of synchronization that offers simple and efficient solutions to several existing problems for which...
US-7,680,986 Practical implementation of arbitrary-sized LL/SC variables
Many conventional lock-free data structures exploit techniques that are possible only because state-of-the-art 64-bit processors are still running 32-bit...
US-7,680,624 Method and apparatus for performing a real-time root-cause analysis by analyzing degrading telemetry signals
One embodiment of the present invention provides a system that performs a real-time root-cause-analysis for a degradation event associated with a component under...
US-7,680,142 Communications chip having a plurality of logic analysers
A communications chip having a plurality of ports. Each port is provided with an interface for attachment to an external communications facility to exchange data...
US-7,679,978 Scheme for screening weak memory cell
A novel scheme for screening weak memory cell includes a cell coupled to a leakage stress delivery circuitry (LSDC), which, in turn, is coupled to an induced...
US-7,679,948 Write and read assist circuit for SRAM with power recycling
A memory circuit for reading and writing data into a SRAM memory array using charge recycling is presented. The write and read circuit includes a cell voltage...
US-7,679,518 Meeting facilitation tool
A meeting facilitation tool may perform and/or facilitate the planning, scheduling, holding, and/or following up of meeting related activities. A meeting...
US-7,678,984 Method and apparatus for programmatically generating audio file playlists
Method and apparatus for programmatically generating interesting audio file playlists. A playlist generation mechanism may use an N-gram model of audio file...
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