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Patent # Description
US-D406,829 Computer screen with an icon
US-D406,828 Icon for a computer screen
US-5,881,303 Multiprocessing system configured to perform prefetch coherency activity with separate reissue queue for each...
A computer system includes multiple processing nodes, each of which is divided into subnodes. Transactions from a particular subnode are performed in the order...
US-5,881,286 Method and apparatus for space efficient inter-process communications
A computer-implemented method and apparatus in a computer system for inter-process communication. A first procedure allocates a first buffer in a first memory...
US-5,881,267 Virtual bus for distributed hardware simulation
Virtual bus stubs, which can be distributed among constituent computers of a computer network, and a central resolver cooperate to simulate a bus which is...
US-5,881,258 Hardware compatibility circuit for a new processor architecture
A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture, efficiently...
US-5,881,241 System for transmitting data packet after matching data packet's routing pattern with predetermined data routes...
Data routing of the present invention is a capability of pre-configuring routes for data traveling through the software or the hardware of a computer system. The...
US-5,881,218 Apparatus for scan test of SRAM for microprocessors having full scan capability
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in...
US-5,881,068 Decode register with scan functionality
A decode register which receives a first plurality of input lines. If the decode register is not in a scan mode during a given clock cycle, the decode register...
US-5,881,067 Flip-flop design and technique for scan chain diagnosis
A modification to conventional scan chain design is disclosed which can identify whether any connection in the scan chain is shorted to the supply voltage or...
US-5,880,746 Apparatus for forming a sum in a signal processing system
According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting a first set...
US-5,880,609 Non-blocking multiple phase clocking scheme for dynamic logic
A non-blocking multiple-phase clocking system for use with dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a...
US-5,880,607 Clock distribution network with modular buffers
A n level clock distribution network for a datapath block includes an external buffer that outputs a clock signal and a datapath block having a logic block and a...
US-5,880,010 Ultrathin electronics
An integrated circuit and associated method for reducing total signal propagation delay as well as power consumption and thermal dissipation. The integrated...
US-5,879,663 Dental composition for dentin hypersensitivity
There is provided a dental composition for relieving dentin hypersensitivity, which occludes dentinal tubules having an opening on the surface of dentin to...
US-5,878,606 Door lock for swinging door
A deadbolt lock system is provided for a swinging door which prevents movement of the deadbolts from a locked position to an unlocked position when the door is...
US-5,878,268 Multiprocessing system configured to store coherency state within multiple subnodes of a processing node
A computer system including one or more processing nodes, each of which includes one or more subnodes is provided. One of the subnodes (the controller subnode)...
US-5,878,264 Power sequence controller with wakeup logic for enabling a wakeup interrupt handler procedure
A power sequence controller contains wakeup logic for responding to each wakeup event signal intercepted by the power sequence controller. The wakeup logic...
US-5,878,252 Microprocessor configured to generate help instructions for performing data cache fills
A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing...
US-5,878,246 System for linking an interposition module between two modules to provide compatibility as module versions change
Apparatus that provides additional flexibility for a computer interface that serves two computer subsystems, when at least one of these subsystems undergoes a...
US-5,878,231 System for packet filtering of data packets at a computer network interface
A system for screening data packets transmitted between a network to be protected, such as a private network, and another network, such as a public network. The...
US-5,878,227 System for performing deadlock free message transfer in cyclic multi-hop digital computer network using a...
In brief summary, the invention provides a new message packet transfer system, which may be used in, for example, a multiprocessor computer system. The message...
US-5,878,050 Method and apparatus for data compare detection of memory errors on a computers memory subsystem
A data compare technique for detecting memory errors on a computer's memory subsystem is disclosed. The technique simulates memory intensive software to...
US-5,877,779 Method and apparatus for efficient rendering of three-dimensional scenes
A method and apparatus for rendering an object or scene from a preselected viewpoint onto a display. The object is represented by a texture map stored in a...
US-5,877,259 Heat sealable adhesive coating composition and process
A heat-sealable adhesive for dissimilar substrates is disclosed comprising an organic solvent suspension of a graft copolymer of an A-B-A terblock copolymeric...
US-5,875,898 Compost purification method and apparatus
Mature particulate compost containing plastic film fragments resulting from the comminution of green waste and the bags containing them, is freed of the plastic...
US-D406,263 Computer generated control panel for a computer monitor
US-5,875,483 Completion unit register file using virtual addresses with qualify and pseudo-address bits
A method and apparatus for generating a qualify bit and detecting matching addresses in the completion unit register file, or annex, of a processor. A qualify...
US-5,875,461 Method of synchronizing one of the objects with one of the threads at a time
A method and apparatus for synchronizing objects is provided. A cache of synchronization constructs is provided and used to synchronize a thread with an object....
US-5,875,443 Internet-based spelling checker dictionary system with automatic updating
A dictionary system has a vendor computer and a plurality of client computers that communicate through the Internet. Each client computer has a word processor...
US-5,875,352 Method and apparatus for multiple channel direct memory access control
An on-chip cache memory is used to provide a high speed access mechanism to frequently used channel state information for operation of a DMA device that supports...
US-5,875,339 Asynchronous arbiter using multiple arbiter elements to enhance speed
An arbiter circuit having a plurality of mutual exclusion (MUTEX) elements is disclosed. Each of the MUTEX elements is coupled to receive a different combination...
US-5,875,316 Method for handling complex instructions in an out-of-order processor
In a processor that executes complex instructions which are expanded into microinstructions prior to execution, non-complex instruction execution is optimized by...
US-5,874,969 Three-dimensional graphics accelerator which implements multiple logical buses using common data lines for...
A 3-D graphics accelerator which includes a command block or preprocessor, a plurality of floating point processors or blocks, and one or more draw processors or...
US-5,874,958 Method and apparatus for accessing information and items across workspaces
A sliding panel configured along an edge of a GUI is associated with an application. When a panel activation event occurs, the panel slides into view, allowing...
US-5,873,258 Sorption refrigeration appliance
A combination heating and cooling apparatus which comprises a compartment into which an item to be heated or cooled may be placed; an electromagnetic wave...
US-D406,124 Icon for a computer screen
US-5,873,117 Method and apparatus for a directory-less memory access protocol in a distributed shared memory computer system
A method in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the...
US-5,873,105 Bounded-pause time garbage collection system and method including write barrier associated with a source...
A write barrier to stores into a partially relocated large or popular memory object facilitates bounded pause time implementations of relocating garbage...
US-5,873,104 Bounded-pause time garbage collection system and method including write barrier associated with source and...
A partially relocated object identifier store including "copy from" identifier and "copy to" identifier storage accessible to write barrier logic allows the...
US-5,873,084 Database network connectivity product
A method and apparatus for publishing and receiving events to a network. A plurality of "publisher" entities publish information and a plurality of "subscriber"...
US-5,872,965 System and method for performing multiway branches using a visual instruction set
An innovative method and system of performing multiway branch operations on a microprocessor architecture which supports single instruction multiple data (SIMD)...
US-5,872,796 Method for interfacing boundary-scan circuitry with linearized impedance control type output drivers
A method for coupling a linear impedance control (LIC) type output driver to IEEE 1149.1 boundary scan circuitry includes entering a boundary scan load mode to...
US-5,872,729 Accumulation buffer method and apparatus for graphical image processing
Various components of a color pixel stored in an accumulation buffer and respective components of a color pixel in a frame buffer are processed substantially...
US-5,872,717 Apparatus and method for verifying the timing performance of critical paths within a circuit using a static...
A method of improving the timing performance of a circuit includes the step of producing a first set of timing results from a static timing analyzer operating on...
US-5,872,526 GPS collision avoidance system
A collision avoidance system for a plurality of vehicles equipped with GPS receivers, each broadcasting current location information to other vehicles and...
US-D405,775 Icon for a computer screen
US-5,870,757 Single transaction technique for a journaling file system of a computer operating system
A single transaction technique for a journaling file system of a computer operating system in which a single file system transaction is opened for accumulating a...
US-5,870,719 Platform-independent, usage-independent, and access-independent distributed quote configuraton system
A platform-independent, usage-independent, location-independent quote configuration system is described. The present invention, operating in a computer network,...
US-5,870,605 Middleware for enterprise information distribution
A method and apparatus for publishing and receiving events to and from a network. A plurality of "publisher" entities publish information and a plurality of...
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