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Patent # Description
US-5,892,510 Field objects and a method for developing a graphical user interface containing the field objects
A graphical user interface (GUI) application program has one or more screens and a number of objects hereinafter "field objects", each field object being...
US-5,892,141 Method and apparatus for analysis of particulate content of gases
A method and apparatus for analysis of particulate content of gases, applicable to the quantitative and qualitative analysis of vehicle engine emissions,...
US-5,891,832 Drilling fluid additive containing a fish oil/glycol mixture and related methods
A drilling fluid additive for use during drilling and excavating applications, the additive comprises a mixture of an oil, an ester alcohol, nonionic surfactant...
US-5,890,169 Disk fragmentation reduction using file allocation tables
A combined file allocation table file system (CFAT file system) uses two or more FAT file systems with different cluster sizes to form a single user visible FAT...
US-5,890,164 Estimating the degree of change of web pages
When monitoring a large number of information sources such as pages on the World Wide Web, a user may not have time to normally look at each source at regular...
US-5,890,008 Method for dynamically reconfiguring a processor
A method and apparatus for dynamically reconfiguring a processor involves placing the processor in a first configuration having a first number (m) of strands...
US-5,889,995 Using constant selectors for method identification
A process for generating method invocation instructions for a source-code program expressed in an object-oriented computer programming language is described. The...
US-5,889,990 Information appliance software architecture with replaceable service module providing abstraction function...
An architecture for an information appliance adapted for a specific application supports a variety of appliance personalities, relying on a single core...
US-5,889,940 System and method for reducing the effects of hardware faults in a computer system employing multiple central...
A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a...
US-5,889,435 On-chip PLL phase and jitter self-test circuit
An ASIC includes a PLL and digital circuitry to quantize and measure phase and average maximum jitter between a system clock input to the PLL, and a ...
US-5,889,417 Apparatus and method for improving the noise immunity of a dynamic logic signal repeater
A dynamic logic signal repeater includes a complementary dynamic logic circuit with an input node to receive an input signal and an output node storing a...
US-5,888,596 Ghost-like decorative object
Decorative structures comprising a flexible sheet-like member simulate universal conceptions of the appearance of floating and fixed ghosts. A structure for...
US-D407,389 Computer screen with a set of icons
US-5,887,181 Method and apparatus for reducing a computational result to the range boundaries of an unsigned 8-bit integer...
The method and apparatus for checking and reducing an intermediate result signal arising from a manipulation of data signals without using conditional branches,...
US-5,887,172 Remote procedure call system and method for RPC mechanism independent client and server interfaces...
A system and method allow client applications to invoke remote procedures on a server application using any of a plurality of remote procedure mechanisms, by...
US-5,887,138 Multiprocessing computer system employing local and global address spaces and COMA and NUMA access modes
A multiprocessing computer system employs local and global address spaces and Non- Uniform Memory Architecture (NUMA) and Cache-Only Memory Architecture (COMA)...
US-5,887,134 System and method for preserving message order while employing both programmed I/O and DMA operations
In a cluster of computer nodes, each node has network interface and at least one processor. Transmission of a multipart message from a first node to a second...
US-5,886,733 Method and apparatus for successive refinement of broadcasted video frames
An apparatus for successive refinement of video frames, and methods of operating the same result in reduced latency for downloading the video frames. The...
US-5,886,712 Data channel extraction in a microprocessor
A method for operating a microprocessor in extracting an arbitrary channel of data from an image of any number of multiple channels with substantially minimized...
US-5,886,697 Method and apparatus for improved graphical user interface having anthropomorphic characters
An intuitive graphical user interface is based upon a geographic map structure, and includes a system for controlling remote external electronic devices. In the...
US-5,886,683 Method and apparatus for eyetrack-driven information retrieval
Apparatus, methods, systems and computer program products are disclosed that determines what information presented on a computer display screen to a user most...
US-5,884,988 Toner-type computer housing for peripherals
A "tower"-type computer has a metal frame or chassis enclosed in an ornamental plastic housing. One side of the plastic housing with an attached metal liner is...
US-5,884,313 System and method for efficient remote disk I/O
When a client computer requests data from a disk or similar device at a server computer, the client exports the memory associated with an allocated read buffer...
US-5,884,288 Method and system for electronic bill payment
A method and system for providing a fully automated electronic bill processing capability that is integrated with banking institutions and their customers is...
US-5,884,223 Altitude sparse aircraft display
A system, method, apparatus, and computer program product for avoiding aircraft collisions with stationary obstacles. The aircraft is provided with a simplified...
US-5,884,100 Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor
A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing...
US-5,884,099 Control circuit for a buffer memory to transfer data between systems operating at different speeds
The present invention relates to a simplified flag control circuitry for use in first in first out (FIFO) memory buffers. The special FIFO memory buffer...
US-5,884,078 System, method and article of manufacture for creating an object oriented component having multiple...
Method, system and article of manufacture for creating an object oriented component having multiple bidirectional ports for use with an object oriented based...
US-5,884,070 Method for processing single precision arithmetic operations in system where two single precision registers are...
In an out-of-order processor having single-precision floating-point registers aliased into double-precision floating-point registers, a single-precision...
US-5,884,025 System for packet filtering of data packet at a computer network interface
A system for screening data packets transmitted between a network to be protected, such as a private network, and another network, such as a public network. The...
US-5,884,024 Secure DHCP server
A preferred embodiment of the present invention includes a method and apparatus for allocating and using IP addresses in a network of client systems. More...
US-5,884,022 Method and apparatus for controlling server activation in a multi-threaded environment
A method and apparatus for controlling server activation. In the prior art, there exists a race condition between the shutting down of an old server and the...
US-5,884,016 System and method for displaying a selected region of a multi-dimensional data object
A data visualization arrangement facilitates the display of a selected region of a multi-dimensional data object in a selected one of a plurality of display...
US-5,883,823 System and method of a fast inverse discrete cosine transform and video compression/decompression systems...
An array of DCT transform coefficients are converted to a two-dimensional array of spatial data in a video compression or decompression system. The array of DCT...
US-5,881,543 Guard assembly for cane cutter
A guard assembly (2) is used to protect the cutter blades (20, 21) of a cane cutter (10). The guard assembly includes a guard body (4) which is mounted to the...
US-D406,829 Computer screen with an icon
US-D406,828 Icon for a computer screen
US-5,881,303 Multiprocessing system configured to perform prefetch coherency activity with separate reissue queue for each...
A computer system includes multiple processing nodes, each of which is divided into subnodes. Transactions from a particular subnode are performed in the order...
US-5,881,286 Method and apparatus for space efficient inter-process communications
A computer-implemented method and apparatus in a computer system for inter-process communication. A first procedure allocates a first buffer in a first memory...
US-5,881,267 Virtual bus for distributed hardware simulation
Virtual bus stubs, which can be distributed among constituent computers of a computer network, and a central resolver cooperate to simulate a bus which is...
US-5,881,258 Hardware compatibility circuit for a new processor architecture
A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture, efficiently...
US-5,881,241 System for transmitting data packet after matching data packet's routing pattern with predetermined data routes...
Data routing of the present invention is a capability of pre-configuring routes for data traveling through the software or the hardware of a computer system. The...
US-5,881,218 Apparatus for scan test of SRAM for microprocessors having full scan capability
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in...
US-5,881,068 Decode register with scan functionality
A decode register which receives a first plurality of input lines. If the decode register is not in a scan mode during a given clock cycle, the decode register...
US-5,881,067 Flip-flop design and technique for scan chain diagnosis
A modification to conventional scan chain design is disclosed which can identify whether any connection in the scan chain is shorted to the supply voltage or...
US-5,880,746 Apparatus for forming a sum in a signal processing system
According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting a first set...
US-5,880,609 Non-blocking multiple phase clocking scheme for dynamic logic
A non-blocking multiple-phase clocking system for use with dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a...
US-5,880,607 Clock distribution network with modular buffers
A n level clock distribution network for a datapath block includes an external buffer that outputs a clock signal and a datapath block having a logic block and a...
US-5,880,010 Ultrathin electronics
An integrated circuit and associated method for reducing total signal propagation delay as well as power consumption and thermal dissipation. The integrated...
US-5,879,663 Dental composition for dentin hypersensitivity
There is provided a dental composition for relieving dentin hypersensitivity, which occludes dentinal tubules having an opening on the surface of dentin to...
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