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Patent # Description
US-5,886,733 Method and apparatus for successive refinement of broadcasted video frames
An apparatus for successive refinement of video frames, and methods of operating the same result in reduced latency for downloading the video frames. The...
US-5,886,712 Data channel extraction in a microprocessor
A method for operating a microprocessor in extracting an arbitrary channel of data from an image of any number of multiple channels with substantially minimized...
US-5,886,697 Method and apparatus for improved graphical user interface having anthropomorphic characters
An intuitive graphical user interface is based upon a geographic map structure, and includes a system for controlling remote external electronic devices. In the...
US-5,886,683 Method and apparatus for eyetrack-driven information retrieval
Apparatus, methods, systems and computer program products are disclosed that determines what information presented on a computer display screen to a user most...
US-5,884,988 Toner-type computer housing for peripherals
A "tower"-type computer has a metal frame or chassis enclosed in an ornamental plastic housing. One side of the plastic housing with an attached metal liner is...
US-5,884,313 System and method for efficient remote disk I/O
When a client computer requests data from a disk or similar device at a server computer, the client exports the memory associated with an allocated read buffer...
US-5,884,288 Method and system for electronic bill payment
A method and system for providing a fully automated electronic bill processing capability that is integrated with banking institutions and their customers is...
US-5,884,223 Altitude sparse aircraft display
A system, method, apparatus, and computer program product for avoiding aircraft collisions with stationary obstacles. The aircraft is provided with a simplified...
US-5,884,100 Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor
A single-chip central processing unit (CPU) includes a processing core and a complete cache-coherent I/O system that operates asynchronously with the processing...
US-5,884,099 Control circuit for a buffer memory to transfer data between systems operating at different speeds
The present invention relates to a simplified flag control circuitry for use in first in first out (FIFO) memory buffers. The special FIFO memory buffer...
US-5,884,078 System, method and article of manufacture for creating an object oriented component having multiple...
Method, system and article of manufacture for creating an object oriented component having multiple bidirectional ports for use with an object oriented based...
US-5,884,070 Method for processing single precision arithmetic operations in system where two single precision registers are...
In an out-of-order processor having single-precision floating-point registers aliased into double-precision floating-point registers, a single-precision...
US-5,884,025 System for packet filtering of data packet at a computer network interface
A system for screening data packets transmitted between a network to be protected, such as a private network, and another network, such as a public network. The...
US-5,884,024 Secure DHCP server
A preferred embodiment of the present invention includes a method and apparatus for allocating and using IP addresses in a network of client systems. More...
US-5,884,022 Method and apparatus for controlling server activation in a multi-threaded environment
A method and apparatus for controlling server activation. In the prior art, there exists a race condition between the shutting down of an old server and the...
US-5,884,016 System and method for displaying a selected region of a multi-dimensional data object
A data visualization arrangement facilitates the display of a selected region of a multi-dimensional data object in a selected one of a plurality of display...
US-5,883,823 System and method of a fast inverse discrete cosine transform and video compression/decompression systems...
An array of DCT transform coefficients are converted to a two-dimensional array of spatial data in a video compression or decompression system. The array of DCT...
US-5,881,543 Guard assembly for cane cutter
A guard assembly (2) is used to protect the cutter blades (20, 21) of a cane cutter (10). The guard assembly includes a guard body (4) which is mounted to the...
US-D406,829 Computer screen with an icon
US-D406,828 Icon for a computer screen
US-5,881,303 Multiprocessing system configured to perform prefetch coherency activity with separate reissue queue for each...
A computer system includes multiple processing nodes, each of which is divided into subnodes. Transactions from a particular subnode are performed in the order...
US-5,881,286 Method and apparatus for space efficient inter-process communications
A computer-implemented method and apparatus in a computer system for inter-process communication. A first procedure allocates a first buffer in a first memory...
US-5,881,267 Virtual bus for distributed hardware simulation
Virtual bus stubs, which can be distributed among constituent computers of a computer network, and a central resolver cooperate to simulate a bus which is...
US-5,881,258 Hardware compatibility circuit for a new processor architecture
A processor which includes separate instruction and data caches and which executes instructions according to a new instruction set architecture, efficiently...
US-5,881,241 System for transmitting data packet after matching data packet's routing pattern with predetermined data routes...
Data routing of the present invention is a capability of pre-configuring routes for data traveling through the software or the hardware of a computer system. The...
US-5,881,218 Apparatus for scan test of SRAM for microprocessors having full scan capability
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in...
US-5,881,068 Decode register with scan functionality
A decode register which receives a first plurality of input lines. If the decode register is not in a scan mode during a given clock cycle, the decode register...
US-5,881,067 Flip-flop design and technique for scan chain diagnosis
A modification to conventional scan chain design is disclosed which can identify whether any connection in the scan chain is shorted to the supply voltage or...
US-5,880,746 Apparatus for forming a sum in a signal processing system
According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting a first set...
US-5,880,609 Non-blocking multiple phase clocking scheme for dynamic logic
A non-blocking multiple-phase clocking system for use with dynamic logic provides clock phases with overlapping evaluation phases to a circuit including a...
US-5,880,607 Clock distribution network with modular buffers
A n level clock distribution network for a datapath block includes an external buffer that outputs a clock signal and a datapath block having a logic block and a...
US-5,880,010 Ultrathin electronics
An integrated circuit and associated method for reducing total signal propagation delay as well as power consumption and thermal dissipation. The integrated...
US-5,879,663 Dental composition for dentin hypersensitivity
There is provided a dental composition for relieving dentin hypersensitivity, which occludes dentinal tubules having an opening on the surface of dentin to...
US-5,878,606 Door lock for swinging door
A deadbolt lock system is provided for a swinging door which prevents movement of the deadbolts from a locked position to an unlocked position when the door is...
US-5,878,268 Multiprocessing system configured to store coherency state within multiple subnodes of a processing node
A computer system including one or more processing nodes, each of which includes one or more subnodes is provided. One of the subnodes (the controller subnode)...
US-5,878,264 Power sequence controller with wakeup logic for enabling a wakeup interrupt handler procedure
A power sequence controller contains wakeup logic for responding to each wakeup event signal intercepted by the power sequence controller. The wakeup logic...
US-5,878,252 Microprocessor configured to generate help instructions for performing data cache fills
A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing...
US-5,878,246 System for linking an interposition module between two modules to provide compatibility as module versions change
Apparatus that provides additional flexibility for a computer interface that serves two computer subsystems, when at least one of these subsystems undergoes a...
US-5,878,231 System for packet filtering of data packets at a computer network interface
A system for screening data packets transmitted between a network to be protected, such as a private network, and another network, such as a public network. The...
US-5,878,227 System for performing deadlock free message transfer in cyclic multi-hop digital computer network using a...
In brief summary, the invention provides a new message packet transfer system, which may be used in, for example, a multiprocessor computer system. The message...
US-5,878,050 Method and apparatus for data compare detection of memory errors on a computers memory subsystem
A data compare technique for detecting memory errors on a computer's memory subsystem is disclosed. The technique simulates memory intensive software to...
US-5,877,779 Method and apparatus for efficient rendering of three-dimensional scenes
A method and apparatus for rendering an object or scene from a preselected viewpoint onto a display. The object is represented by a texture map stored in a...
US-5,877,259 Heat sealable adhesive coating composition and process
A heat-sealable adhesive for dissimilar substrates is disclosed comprising an organic solvent suspension of a graft copolymer of an A-B-A terblock copolymeric...
US-5,875,898 Compost purification method and apparatus
Mature particulate compost containing plastic film fragments resulting from the comminution of green waste and the bags containing them, is freed of the plastic...
US-D406,263 Computer generated control panel for a computer monitor
US-5,875,483 Completion unit register file using virtual addresses with qualify and pseudo-address bits
A method and apparatus for generating a qualify bit and detecting matching addresses in the completion unit register file, or annex, of a processor. A qualify...
US-5,875,461 Method of synchronizing one of the objects with one of the threads at a time
A method and apparatus for synchronizing objects is provided. A cache of synchronization constructs is provided and used to synchronize a thread with an object....
US-5,875,443 Internet-based spelling checker dictionary system with automatic updating
A dictionary system has a vendor computer and a plurality of client computers that communicate through the Internet. Each client computer has a word processor...
US-5,875,352 Method and apparatus for multiple channel direct memory access control
An on-chip cache memory is used to provide a high speed access mechanism to frequently used channel state information for operation of a DMA device that supports...
US-5,875,339 Asynchronous arbiter using multiple arbiter elements to enhance speed
An arbiter circuit having a plurality of mutual exclusion (MUTEX) elements is disclosed. Each of the MUTEX elements is coupled to receive a different combination...
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