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Load instruction steering in a dual data cache microarchitecture
An apparatus for executing an instruction is provided. The instruction loads data into one of a plurality of registers in a register file and is in a first group...
Maintaining a sequential store order (SSO) in a non-SSO machine
In a multiprocessor system, a method, apparatus, and article of manufacture for maintaining the proper sequence of store/write operations between multiple...
Mutual exclusivity circuit for use in test pattern application scan
A circuit for locally ensuring mutual exclusivity of selected signals during scan testing is coupled between an IEEE 1149.1 TAP controller and a conventional...
Method for fast rendering of three-dimensional objects by generating
lists of like-facing coherent primitives
A method and apparatus for fast rendering of objects or scenes on a display controlled by a computer system. The scene to be rendered is stored as a series of...
Method and apparatus for eyetrack-driven captioning
Apparatus, methods, systems and computer program products are disclosed that detect when a user is interested in information presented on a display device. The...
Drift canceling method and apparatus for analog to digital converters
A drift canceling method and apparatus is used in conjunction with an analog to digital converter. The drift canceling method and apparatus analyzes the duty...
Edge-triggered staticized dynamic flip-flop with scan circuitry
A flip-flop circuit with scan circuitry for use with static logic gates includes a dynamic input stage and a static output stage. The dynamic input stage is...
Differential high speed driver for low voltage operation
A driver includes first and second input terminals for receiving first and second input voltages, respectively, of a differential input signal, first and second...
Method and system for efficient organization of selectable elements on a
graphical user interface
A method and system for organizing selectable elements on a graphical user interface (GUI). Initially, the method provides at least two selectable elements for...
Multiprocessor system having mapping table in each node to map global
physical addresses to local physical...
In a multiprocessor computing system, virtual memory addresses are mapped to local physical memory addresses of an attraction memory, containing a replication of...
Multiprocessing system employing a coherency protocol including a reply
A multiprocessing computer system employing a three-hop communications protocol including a reply count communication. When a request is sent by a requesting...
Methods and apparatus for fixed canvas presentations detecting canvas
specifications including aspect ratio...
Apparatus, methods, systems, and computer program products are disclosed for displaying fixed canvas presentations, defined using HTML data, on computer output...
Selective radio frequency pest control apparatus
This application discloses an apparatus and method for generating and radiating energy at specific radio frequency wavelengths known to adversely affect the...
Method and apparatus for resolving data references in generated code
A hybrid compiler-interpreter comprising a compiler for "compiing" source program code, and an interpreter for interpreting the "compiled" code, is provided to a...
Method and system for synchronizing the execution of events
An embodiment of the present invention provides an improved method and system for synchronizing the execution of two or more events used to test a software...
Maintaining data coherency between a primary memory controller and a
backup memory controller
A fault tolerant memory control system is provided for a computer system having a host processor, a memory and a system interconnect. The memory control system...
A sticky leveler utilizing a window detection technique to preserve the relatively small level changes of an audio signal. The sticky leveler includes a voltage...
Method and apparatus for scan test of SRAM for microprocessors without
full scan capability
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in...
Method for handling an underflow condition in a processor
A method for handling an underflow condition in a processor is disclosed. A first plurality of signal data is packed into a first memory location so as to form a...
Method and apparatus for simultaneously displaying graphics and video
data on a computer display
A method and apparatus for displaying graphics data and video data, such as a video window, on a computer display. A graphics adapter chip stores graphics pixel...
Cross-domain data transfer using deferred page remapping
A cross-domain data transfer technique is disclosed in which page remapping operations are eliminated in situations where physical memory addresses can be passed...
Icon for a computer screen
Slip-on wrist case for hiking/outdoor instruments such as thermometers,
compasses, clocks, signal mirrors,...
Table top rim
Multiple bus bridge system for maintaining a complete order by delaying
servicing interrupts while posting...
A system for maintaining completion order in a multiple bus system including a bridge that posts write data includes logic units for implementing a DRAIN/EMPTY...
Apparatus and method for computing a difference in a digital processing
According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting from a first...
Device for enabling listeners to preview music recordings
A bar code reader, a wireless transceiver, an earphone jack and a battery are integrated into a pen sized device. The bar code reader is used to scan the product...
Support for printed circuit board during processing
During processing, such as wave soldering, it is necessary to support a printed circuit board (PCB) above a pallet or carrier without sagging. A support rod has...
System and method for parallel execution of memory transactions using
multiple memory models, including SSO,...
A data processor supports the use of multiple memory models by computer programs. At a device external to a data processor, such as a memory controller, memory...
Deterministic distributed multi-cache coherence method and system
An efficient streamlined coherent protocol for a multi-processor multi-cache computing system. Each subsystem includes at least one processor and an associated...
Method and apparatus for preventing a race condition and maintaining
cache coherency in a processor with...
An integrated processor includes an on-chip integrated input/output (IO) system (which does not have a on-chip bus) to handle direct memory access (DMA)...
Method and apparatus that detects and tolerates inconsistencies between
the cache and main memory, and the...
Inconsistencies between cache and memory in a memory system operating in a computer are traced and corrected. A cache entry is checked against a counterpart...
Efficient allocation of cache memory space in a computer system
An efficient cache allocation scheme is provided for both uniprocessor and multiprocessor computer systems having at least one cache. In one embodiment, upon the...
Flushing of cache memory in a computer system
An efficient streamlined cache coherent protocol for replacing data is provided in a multiprocessor distributed-memory computer system. In one implementation,...
Hybrid NUMA COMA caching system and methods for selecting between the
The present invention provides a hybrid Non-Uniform Memory Architecture (NUMA) and Cache-Only Memory Architecture (COMA) caching architecture together with a...
System and method for swapping blocks of tagged stack entries between a
tagged stack cache and an untagged main...
A computer system has a CPU, a stack cache and a main memory. The main memory is a conventional untagged memory, where each memory location is a word having a...
Method and apparatus for representing recurring events
A method and apparatus for representing and storing the schedules of recurring events. The schedules are represented by recurrence rules generated according to a...
Multiprocessing system configured to perform efficient block copy
A computer system optimized for block copy operations is provided. In order to perform a block copy from a remote source block to a local destination block, a...
Processor complex for executing multimedia functions
A computer processor complex including a hardware processor coupled to a multimedia coprocessor is provided. This computer processor complex is capable of...
Method and apparatus for interrupt communication in packet-switched
microprocessor-based computer system
An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt...
Method and apparatus for refreshing file locks to minimize conflicting
accesses to data files
A system for generating and maintaining lock files to inhibit conflicting requests for data files. A first process that accesses a data file generates a lock...
Method and apparatus for efficient evaluation of semantic attributes in
A method and apparatus for compiling source code that pre-evaluates certain semantic attributes during syntactical analysis. The invention performs certain type...
Interface for telecommunications network management
An applications programming interface 20 to a telecommunications management network includes a command language interpreter 24 and a compiler 40. A command...
Test support tool system and method
A test support tool system and method produce software test programs from a logical description of selected software. Test programs are created by producing a...
Spell checking universal resource locator (URL) by comparing the URL
against a cache containing entries...
A cache, storing misspelled or otherwise incorrect network addresses from a plurality of users and associated correct network addresses, is maintained at a proxy...
Boundary-scan circuit for use with linearized impedance control type
A circuit for coupling a LIC driver to a IEEE 1149.1 boundary scan implementation includes a logic circuit that converts the data and oe signals of the IEEE...
Signal interpolation and decimation exploiting filter symmetry
Symmetry in a filter is used to reduce the complexity of an interpolator or a decimator. A weight filter matrix which includes L=(N-1)M+K weights is divided into...
Hard disk drive heat sink
A plate formed with louvers and a depression to heat engage a hard disk drive motor is attached to such a drive. Heat from the motor is transferred to the plate....
Field objects and a method for developing a graphical user interface
containing the field objects
A graphical user interface (GUI) application program has one or more screens and a number of objects hereinafter "field objects", each field object being...