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Patent # Description
US-5,943,040 Graphical image reformatting
A number of multiple-band pixels are stored in a number of data words and the multiple-band pixels are merged and sorted such that all components of each band of...
US-5,942,947 Current-regulated, voltage-controlled oscillator with duty cycle correction
A voltage controlled current source provides controlled current to a current controlled oscillator in a high frequency phase-locked loop clock generator. The...
US-5,942,919 Differential receiver including an enable circuit
A receiver is provided which quickly and efficiently recognizes signals by including with the receiver a resolving circuit which is coupled to a node control...
US-5,942,918 Method for resolving differential signals
A method for resolving differential signals is provided which quickly and efficiently recognizes signals by resolving differences between the signals using a...
US-5,942,781 Tunable threshold SOI device using back gate well
A fully depleted SOI device includes a semiconductor substrate and a conductive well of a first conductivity type formed in a principal surface of the...
US-5,942,777 Memory device including a memory array having a combination of trench capacitor DRAM cells and stacked...
A memory device is presented including a memory array having both trench capacitor and stacked capacitor DRAM cells. The trench and stacked capacitor DRAM cells...
US-5,942,467 Drilling fluid system containing a combination of hydrophilic carbon black/asphaltite and a refined fish...
A drilling fluid system that combines a carbon black/asphaltite/lignite mixture with a fish oil/glycol mixture; and a method for manufacturing a drilling fluid...
US-5,941,999 Method and system for achieving high availability in networked computer systems
The present invention provides a method and system for achieving high availability in networked computer systems. The computer system includes a client node, two...
US-5,941,985 Branch instruction prediction method
The outcome of a given branch instruction is predicted using early and late branch history addressing modes. In an early addressing process, a first subset of...
US-5,941,977 Apparatus for handling register windows in an out-of-order processor
In a processor speculatively executing instructions which specify logical addresses, a method and apparatus for speculatively converting logical addresses to...
US-5,941,954 Network message redirection
A method for redirecting communication on a network between a client and a network resource includes executing a software program, the software program...
US-5,940,860 Methods and apparatus for substantially memory-less coherence transformer for connecting computer node...
An apparatus and method for facilitating the sharing of memory blocks between a computer node and an external device irrespective whether the external device and...
US-5,940,855 System and method for determining relative cache performance in a computer system
A system, method and computer program product which determines the relative performance of a local cache and renders the resultant performance increase (or in...
US-5,940,827 Methods and apparatus for managing a database in a distributed operating environment
A variety of methods and apparatus for managing a database in a object oriented environment are disclosed. According to the present invention, a database is...
US-5,940,613 Method for creating a single binary virtual device driver for a windowing operating system
A method for creating a virtual device driver that runs under both Windows 3.x and Windows 95 operating systems is disclosed. There are two basic obstacles to be...
US-5,940,601 Control circuit and method for a first-in first-out data pipeline
Several designs of a stage for use in a FIFO pipeline are disclosed. Each stage includes a latch that is capable of latching a data element and capable of...
US-5,940,401 Carrier extension for gigabit/second ethernet networks operable up to at least 200 m distances
Transmission rates of 1 Gb/sec. at up to at least 200 m diameter distances are achieved in an Ethernet environment by functionally decoupling frame size to...
US-5,940,078 Method and apparatus for changing the appearance of icon images on a computer display monitor
Methods and apparatuses for altering the appearance of an icon box when an event effecting the icon box occurs are disclosed. In one embodiment, a pointer...
US-5,939,782 Package construction for integrated circuit chip with bypass capacitor
An integrated circuit assembly includes an integrated circuit die having a first face, a second face and a perimeter. The second face bears a plurality of...
US-5,938,761 Method and apparatus for branch target prediction
One embodiment of the present invention provides a method and an apparatus for predicting the target of a branch instruction. This method and apparatus operate...
US-5,938,756 Central processing unit with integrated graphics functions
The integer execution unit (IEU) of a central processing unit (CPU) is provided with a graphics status register (GSR) for storing a graphics data scaling factor...
US-5,938,736 Search engine architecture for a high performance multi-layer switch element
A multi-layer switch search engine architecture is provided. According to one aspect of the present invention, a switch fabric includes a search engine, and a...
US-5,938,732 Load balancing and failover of network services
A system and method for many-to-many failover and load balancing establishes a plurality of service groups for providing desired computing services. Each service...
US-5,937,587 Garage door decorative cover assembly
A garage door decorative cover assembly for use on an exterior surface of a garage door made of a plurality of door panels permitted to rotate relative to each...
US-5,937,436 Network interface circuit including an address translation unit and flush control circuit and method for...
A network interface circuit including an address translation unit and a flush check circuit, and a method for checking for an invalid address translation within...
US-5,937,417 Tooltips on webpages
A method and apparatus that allows a Web page designer to specify tooltips for his Web page. Tooltips are text areas that display automatically when the user...
US-5,937,187 Method and apparatus for execution and preemption control of computer process entities
In a multiprocessing computer system, a schedulable process entity (such as a UNIX process, a Solaris lightweight process, or a Windows NT thread) sets a memory...
US-5,937,177 Control structure for a high-speed asynchronous pipeline
Apparatus is disclosed for asynchronously controlling a pipeline. The control circuitry includes an alternating chain of control circuits and detection circuits....
US-5,936,873 Single ended match sense amplifier
A single-ended match sense amplifier is provided for use in a translation lookaside buffer. The translation lookaside buffer includes a CAM array for storing x...
US-5,936,636 Encoding schemes
Translation between a character encoding scheme used by an application and a font encoding scheme used by a character drawing routine may be controlled...
US-5,935,249 Mechanism for embedding network based control systems in a local network interface device
A secure, trusted network management function embedded within a network interface device is provided. The network interface device connects a host computer to a...
US-5,935,242 Method and apparatus for initializing a device
A system is provided for rebooting a computer having a volatile memory device capable of storing operating information. The system reboots the computer using the...
US-5,935,238 Selection from multiple fetch addresses generated concurrently including predicted and actual target by...
A microprocessor is provided with an instruction fetch mechanism that simultaneously predicts multiple control-flow instructions. The instruction fetch unit...
US-5,934,018 Molded plant tray
A molded plant tray is provided in the form of a unitary molded plastic member formed of relatively light foamed plastic and having downwardly extending tapered...
US-5,933,844 Write through virtual cache memory, alias addressing, and cache flushes
In a computer system comprising a CPU, a cache memory and a main memory wherein the cache memory is virtually addressed, and some of the virtual addresses are...
US-5,933,644 Method and apparatus for conflict-based block reordering
A method and apparatus for ordering blocks of code by a compiler. The compiler generates a conflict graph in accordance with the blocks of a computer program...
US-5,933,635 Method and apparatus for dynamically deoptimizing compiled activations
Methods and apparatus for dynamically deoptimizing a frame in a control stack during the execution of a computer program are disclosed. The described methods are...
US-5,933,627 Thread switch on blocked load or store using instruction thread field
A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or...
US-5,933,160 High-performance band combine function
A high-performance band combine function to transform a source image of n bands to a destination image of m bands. A source image vector is multiplied with a...
US-5,933,157 Central processing unit with integrated graphics functions
The integer execution unit (IEU) of a central processing unit (CPU) is provided with a graphics status register (GSR) for storing a graphics data scaling factor...
US-5,933,153 Mesh buffer for decompression of compressed three-dimensional graphics data
Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state...
US-5,933,142 User-controllable persistent browser display pages
The present invention provides a user control mechanism for selectively retaining for display a document obtained from a network. The user control is located as...
US-5,933,140 Child window containing context-based help and a miniaturized web page
A non-interruptive, context-based help system and method for use in a WorldWideWeb based environment includes links to help software that, when activated, tracks...
US-5,933,038 Flip-flop with logic function incorporated therein with minimal time penalty
A flip-flop circuit for use with logic gates includes a dynamic input stage and a static output stage. The flip-flop receives a single phase which defines a...
US-5,933,021 Noise suppression method and circuits for sensitive circuits
Circuits and methods of suppressing noise on a signal line are disclosed. A noise suppression pull-down circuit is coupled to a signal line which couples the...
US-5,932,061 Board Level Decapsulator
A system that decapsulates an integrated circuit package while the package is mounted to a printed circuit board. The system includes a tray that supports a...
US-5,931,945 Graphic system for masking multiple non-contiguous bytes having decode logic to selectively activate each of...
A partial store instruction and associated logic for storing selected bytes of a group of bytes in a register to a designated memory location. A mask in a...
US-5,931,938 Multiprocessor computer having configurable hardware system domains
Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers...
US-5,931,926 Method and apparatus for dynamically calculating degrees of fullness of a synchronous FIFO
An interface circuit, coupled between a first circuitry that is synchronous to a first clock (sclk) and a second circuitry that is synchronous to a second clock...
US-5,931,922 Media server system for preventing FIFO buffer underflow during multiple channel startup by waiting until...
A media server system and method for reducing the probability of data starvation or underflow in a media server system. The media server system preferably...
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