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Patent # Description
US-5,920,722 System and process for efficiently determining absolute memory addresses for an intermediate code model
A system and process for efficiently determining absolute addresses for an intermediate code model of an address space are described. A processor interfaces to a...
US-5,920,566 Routing in a multi-layer distributed network element
A multi-layer distributed network element for relaying packets according to known routing protocols. A distributed architecture of multiple subsystems delivers...
US-5,920,218 Single-phase edge-triggered dual-rail dynamic flip-flop
A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input...
US-5,920,215 Time-to-charge converter circuit
In a charge pump the noise due to switching transients on the input pulse lines is kept to extremely low levels by translating input up/down pulses into small...
US-5,919,265 Source synchronization data transfers without resynchronization penalty
A system clock generator for a computer system to efficiently transfer data from a source subsystem to a destination subsystem of the computer system. The system...
US-D411,774 Disposable package and dispenser
US-5,918,245 Microprocessor having a cache memory system using multi-level cache set prediction
A cache structure for a microprocessor which provides set-prediction information for a separate, second-level cache, and a method for improving cache accessing,...
US-5,918,034 Method for decoupling pipeline stages
The present invention solves the problems associated with the prior art by decoupling the issuing of instructions from their dispatch into their respective...
US-5,917,740 Apparatus for reducing a computational result to the range boundaries of a signed 16-bit integer in case of...
The present invention is directed to checking and reducing an intermediate signal arising from a manipulation of 16-bit signed data signals without using...
US-5,917,355 Edge-triggered staticized dynamic flip-flop with conditional shut-off mechanism
A single phase edge-triggered staticized dynamic flip-flop circuit for use with dynamic logic gates includes a dynamic input stage and a static output stage. The...
US-5,916,259 Coaxial waveguide applicator for an electromagnetic wave-activated sorption system
The present invention is directed to a coaxial waveguide applicator for an electromagnetic wave-activated sorption system which comprises at least one sorber...
US-D411,663 Gripper portfolio
US-D411,527 Icon for a computer screen
US-D411,526 Icon for a computer screen
US-5,915,255 Method and apparatus for referencing nodes using links
Apparatus, methods, systems, and computer program products are disclosed that use a link to access nodes in a generational garbage collected heap. The creation...
US-5,915,096 Network browsing system and method
A network browser system facilitates browsing of resources in a network, each of the resources having a respective network address. The network browser system...
US-5,914,724 Lighting unit for a three-dimensional graphics accelerator with improved handling of incoming color values
A lighting unit which exhibits improved handling of incoming color values corresponding to a polygon. The lighting unit includes an input buffer for storing a...
US-5,914,723 Method and system for converting images in computer systems
The present invention provides a method and system in computer systems for converting an original image into another image having fewer colors than the original...
US-5,914,675 Emergency locator device transmitting location data by wireless telephone communications
A portable emergency locator device includes a global positioning system (GPS) receiver generating location data and a wireless telephone transceiver for...
US-5,913,218 System and method for retrieving and updating configuration parameter values for application programs in a...
A configuration parameter value access system used in connection with a computer system performs an access operation in connection with a configuration parameter...
US-5,913,065 System, method and article of manufacture for creating hierarchical folder components for use in a java...
Method, system and article of manufacture for creating hierarchical folder components for use with in holding other object oriented based components, including...
US-5,913,064 Method for generating instructions for an object-oriented processor
A method for generating code for an object-oriented processor is disclosed. An instruction table is initialized to include a plurality of instructions for an...
US-5,912,995 Method and apparatus for rotating or transposing a binary image
A method which may be implemented in a library routine for performing an image transformation. First, a plurality of groups of bits are selected, with each group...
US-5,912,906 Method and apparatus for recovering from correctable ECC errors
On-chip delivery of data from an on-chip or off-chip cache is separated into two buses. A fast fill bus provides data to latency critical caches without ECC...
US-5,912,799 Multiple disk drive storage enclosure with ventilation
An enclosure is assembled from metal-plated rigid structural foam plastic components to house in minimal space in many hard disk drives. Major components,...
US-5,912,677 Method for forming a sum in a signal processing system
According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting a first set...
US-5,912,673 Graphical image convolution using multiple pipelines
A parallel processor which is capable of partitioned multiplication and partitioned addition operations convolves multiple pixels in parallel. The parallel...
US-5,912,574 Dual loop PLL with secondary loop to achieve 50% duty cycle
A phased lock loop (PLL) clock circuit generates a clock signal at 1x the desired clock frequency while maintaining substantially a 50% duty cycle. A first loop...
US-5,912,567 Dual differential comparator with weak equalization and narrow metastability region
In a sample-and-hold circuit, an input is tracked at an output during a tracking period and the input is held during an holding period, the tracking period and...
US-5,912,563 Trinary signal apparatus and method
Extended trinary signal apparatus includes window comparator logic having first and second inputs for first and second trinary input signals, wherein each the...
US-5,911,778 Processing system security
For controlling access to a system resource in a processing system, reprogrammable logic located between a bus and the resource is programmed in a first mode to...
US-5,911,596 Strain relief apparatus and methods therefor
An apparatus for securing a conductor to a circuit board. The conductor is configured for being soldered to the circuit board through a first aperture in the...
US-D411,077 Handle for cooking utensil
US-D410,911 Icon for a computer screen
US-5,911,144 Method and apparatus for optimizing the assignment of hash values to nodes residing in a garbage collected heap
Apparatus, methods, systems, and computer program products are disclosed that generate a hash value for a node allocated from a generational garbage collected...
US-5,911,081 Method and apparatus for selectively inhibiting power shutdowns based upon the number of power shutdowns that...
Disclosed is a process and apparatus for controlling a power shutdown of an electrical device. The operations for controlling a power shutdown include ...
US-5,911,071 Persistent programming system and method for deploying self-containing executable applications
The invention creates a self-contained executable application. A compiler compiles an application including main source code and initialization code to generate...
US-5,911,052 Split transaction snooping bus protocol
A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other...
US-5,911,041 Method for generalized windows application install testing for use with an automated test tool
A computer implemented method and computer system for testing a target software product is presented. The method includes constructing a finite state machine in...
US-5,910,910 Circuit and method for rapid calculation of quotients and square roots
A circuit and method for accelerating the division algorithm and square root operations relating to integers or floating-point numbers. Minimization of the...
US-5,909,697 Reducing cache misses by snarfing writebacks in non-inclusive memory systems
A non-inclusive multi-level cache memory system is optimized by removing a first cache content from a first cache, so as to provide cache space in the first...
US-5,909,695 Maximal concurrent lookup cache for computing systems having a multi-threaded environment
A multi-threaded processing system has a cache that is commonly accessible to each thread. The cache has a plurality of entries for storing items, each entry...
US-5,909,686 Hardware-assisted central processing unit access to a forwarding database
A method and apparatus for providing hardware-assisted CPU access to a forwarding database is described. According to one aspect of the present invention, a...
US-5,909,579 Method and apparatus for encoding and decoding delta encoded information to locate live pointers in program...
Live pointer information for a stream of bytecodes is precomputed for each bytecode. The precomputed full live pointer information is stored only for bytecodes...
US-5,909,451 System and method for providing scan chain for digital electronic device having multiple clock domains
A digital electronic circuit device comprises a plurality of circuit elements, a scan chain establishment element, and a unitary clock domain establishment...
US-5,908,471 Diagnostic arrangement for digital computer system
A diagnostic subsystem is used in a digital device in a digital computer system includes a diagnostic register, a device output control circuit and a diagnostic...
US-5,907,847 Method and apparatus for coupling object state and behavior in a database management system
A method and apparatus for coupling object state and behavior in a DBMS is provided such that an object's class definition, behavior information, and state...
US-5,907,708 System and method for facilitating avoidance of an exception of a predetermined type in a digital computer...
A system for avoiding exceptional conditions during execution of a program comprises an execution environment for executing the program and a fix-up code...
US-5,907,705 Computer implemented request to integrate (RTI) system for managing change control in software release stream
Change control in a software release stream is managed by a computer implemented Request To Integrate (RTI) system, including at least one user unit having an...
US-5,907,695 Deadlock avoidance mechanism for virtual bus distributed hardware simulation
To simulate a bus of a circuit, a number of virtual bus stubs ("VBSs") each post simulated bus signals as a single step and execution of the simulation system...
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