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Wicker and wrought iron chair
Wicker and wrought iron chair
Method, apparatus and computer program product for optimizing registers
in a stack using a register allocator
Apparatus, methods and computer program products are disclosed that enable a compiler to generate efficient code to access stack registers on a register stack....
Microprocessor for performing unsigned operations with signed
A microprocessor operable to transform unsigned data to a signed format so that the unsigned data can be processed by signed instructions. In particular, a...
Microprocessor for performing signed operations with unsigned
A mechanism in a microprocessor to transform signed data to an unsigned format so that the signed data can be processed by unsigned instructions. In particular,...
Dynamic linkable labels in a network browser page
In a computer network where remote user stations retrieve information from other sites in the network, a method and apparatus for creating and displaying dynamic...
Method and apparatus for authenticating on-line transaction data
The present invention comprises a method and apparatus for authenticating data related to on-line transactions. The invention utilizes a user-customized...
Method of implementing parameterized types to be compatible with
existing unparameterized libraries
A method and apparatus for generating code using parameterized classes which is compatible with an existing class library that was previously generated using...
Method for reducing circuit area by grouping compatible storage devices
In a control block design methodology, a control block is designed, synthesized, and laid out. The control block includes one or more storage devices, such as...
Output driver with overshoot and undershoot protection
A output driving circuit having an output driving element, an overshoot protection mechanism, and an undershoot protection mechanism. When the overshoot...
Three-dimensional graphics accelerator with an improved vertex buffer
for more efficient vertex processing
A vertex accumulation buffer for improved three-dimensional graphical processing is disclosed. The accumulation buffer may include two individual buffers...
Automatically generated content-based history mechanism
A history mechanism is provided in which user data, which represents signals generated by a user, are stored for subsequent recall and regeneration in a history...
Non-blocking delayed clocking system for domino logic
A non-blocking multiple-phase clocking system for use with domino-type dynamic logic provides clock phases with overlapping evaluation phases to a circuit...
Method for handling data cache misses using help instructions
A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing...
Leasing for failure detection
A system for using a lease to detect a failure and to perform failure recovery is provided. In using this system, a client requests a lease from a server to...
Method and apparatus for constructing stable iterators in a shared data
In a distributed object system, a stable object iterator provides a list of all persistent objects within a collection of objects. A plurality of iterators are...
Trunking support in a high performance network device
A method and apparatus for providing trunking support in a network device is provided. According to one aspect of the present invention, a network device...
Lighting unit for a three-dimensional graphics accelerator with improved
processing of multiple light sources
A lighting unit for improved processing of multiple light sources. The lighting unit includes an input buffer for receiving one or more attributes corresponding...
Low phase noise LC oscillator for microprocessor clock distribution
A microprocessor includes an on-chip low phase noise CMOS LC capacitance oscillator. The LC oscillator is relatively insensitive to power supply fluctuations. In...
Method and apparatus for scan test of SRAM for microprocessor without
full scan capability
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in...
Method and apparatus for fully controllable integrated circuit internal
A clock generation and control circuit to debug an integrated circuit includes a multiplexer connected to a set of input lines that carry a set of clock signals....
Method for computing a difference in a digital processing system
According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting from a first...
Processor with accelerated array access bounds checking
An array boundary checking apparatus is configured to verify that a referenced element of an information array is within a maximum array size boundary value and...
System and method for message transmission between network nodes using
A first computer sends a sequence of messages to a second computer using remote write operations to directly store each message in a corresponding memory...
Highly-available distributed cluster configuration database
The cluster configuration database is a distributed configuration database wherein a consistent copy of the configuration database is maintained on each active...
Method and apparatus for client-sensitive name resolution using DNS
A method and apparatus for performing client-sensitive DNS translations includes the steps of receiving a translation request by a DNS server. The DNS server...
System for generating and graphically displaying call stack information
for processing elements in a parallel...
A system for generating a "where graph" for a parallel processing system comprising a parallel processing array controlled by a control processor. The processing...
Mechanism for packet field replacement in a multi-layer distributed
A multi-layer distributed network element for relaying packets according to known routing protocols. A distributed architecture of multiple subsystems delivers...
Single ended read scheme with global bitline of multi-port register file
A read system for a multi-ported register file includes a segmented bit line coupled to a global bit line. Each local bit line segment is coupled to a sub-set of...
Rapid computation of local eye vectors in a fixed point lighting unit
A rapid method for calculating a local eye vector in a fixed point lighting unit. For a given triangle primitive which is to be projected into a given viewport...
Apparatus and method for controlling data, address, and enable buses
within a microprocessor
A CPU includes a common bus, a bus interface unit (BIU), and a plurality of module units. The BIU includes a decode stage, an arbitration stage, and a control...
Computer component cooling fan closure device and method thereof
Disclosed is a system for assisting in preventing over heating of the internal electrical components of a computer in the event of a failure of one of the...
Method and apparatus for generating small, optimized color look-up tables
In a computer graphics windowing system including a color map, a method for managing palette color value contents of the color map. Input color values are...
Method of charging a dynamic node
An apparatus and method for resetting a dynamic logic circuit is disclosed. The apparatus includes an input circuit coupled to a plurality of input nodes wherein...
Pusher switch light socket
a pusher switch light socket essentially relates to one to provide a terminal for receiving and holding in position of lead-in wires, one lead-in wire support is...
Mixed execution stack and exception handling
Systems and methods for implementing an execution stack which stores frames for functions written in multiple programming languages are provided. The frames for...
Digital data processing system including efficient arrangement to
support branching within trap shadows
A digital computer includes an efficient mechanism by which an exception handler can traverse the instruction stream in a reverse direction to identify the...
Pipelined stack caching circuit
A stack management unit includes a stack cache to accelerate data retrieval from a stack and data storage into the stack. The stack management unit also includes...
Method and apparatus for enabling application programs to communicate
with network clients and servers
A method for enabling an application program to communicate with a network server, includes the steps of downloading a document from a document server to the...
Register allocation via selective spilling
An approach for allocating a set of virtual registers to a set of physical registers using selective spilling is described. A set of code and a spill variable...
Methods, apparatus and data structures for managing objects
A variety of methods, apparatus, and data structures for managing transient and persistent distributed objects are disclosed. Objects for use as object...
Spare repeater amplifiers for long lines on complex integrated circuits
An IC includes a plurality of functional blocks each having a discrete block-level architecture. The functional blocks are connected to one another via metal...
Variable length decoding using lookup tables
One embodiment of the present invention provides a method and an apparatus for decoding a variable length code using lookup tables. This embodiment improves...
Circuit and method for selectively enabling ECL type outputs
A clock circuit for selectively enabling a clock signal to be propagated, via a transmission line, to an option module when the module is coupled to the clock...
Absorbent pair refrigerant system
An absorbent pair refrigeration system comprising a source of liquid refrigerant; an evaporator for transforming the liquid refrigerant into vapor refrigerant at...
Password helper using a client-side master password which automatically
presents the appropriate server-side...
A user operating a client system may access a plurality of remote servers requiring passwords for access by employing a master password. The master password is...
Apparatus for restraining over-eager load boosting in an out-of-order
machine using a memory disambiguation...
A system for restraining over-eager boosting of load instructions past store instructions in an out-of-order processor. The system comprises a memory...