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Patent # Description
US-6,023,271 Framework for binding data viewers/data manipulation with one to many objects through introspection
Systems and methods for programming applications with GUIs in accordance that do not require time-consuming and error-prone custom coding of GUI/internal...
US-6,023,179 Method of implementing a scan flip-flop using an edge-triggered staticized dynamic flip-flop
A method of implementing a scan flipp for use with logic gates includes configuring the flip-flop into a scan mode or data mode. Then the flip-flop enters the...
US-6,021,491 Digital signatures for data streams and data archives
Methods, apparatuses and products are provided for verifying the authenticity of data within one or more data files. Each data file is provided with an...
US-6,021,469 Hardware virtual machine instruction processor
A hardware virtual machine instruction processor directly executes virtual machine instructions that are processor architecture independent. The hardware...
US-6,021,446 Network device driver performing initial packet processing within high priority hardware interrupt service...
A network device such as an Asynchronous Transfer Method (ATM) device with a high level interrupt which begins processing a packet and transfers process control...
US-6,021,443 Systems, software, and methods for routing events among publishers and subscribers on a computer network
A method and apparatus for publishing and receiving events to and from a network. A plurality of "publisher" entities publish information and a plurality of...
US-6,021,435 Apparatus and method for displaying enhanced hypertext link anchor information regarding hypertext page...
A hypertext browsing system collects information about availability of links and display this link availability information. A user can then readily determine...
US-6,021,414 Single transaction technique for a journaling file system of a computer operating system
A single transaction technique for a journaling file system of a computer operating system in which a single file system transaction is opened for accumulating a...
US-6,021,273 Interpreter generation and implementation utilizing interpreter states and register caching
Systems and methods for increasing the execution speed of interpreted programs which utilize an operand stack are provided. The value for the top of the operand...
US-6,021,132 Shared memory management in a switched network element
A method and apparatus for shared memory management in a switched network element is provided. According to one aspect of the present invention, a shared memory...
US-6,020,939 Method and apparatus for reducing electromagnetic interference radiated by cathode ray tube displays
Electromagnetic interference ("EMI") is reduced in a CRT video display system by spreading-out the EMI-producing spectra present in the video pixel data and/or...
US-6,020,901 Fast frame buffer system architecture for video display system
A fast frame buffer system and architecture supports preferably 24-bit capability and includes an integer rendering pipeline, especially useful for...
US-6,020,881 Graphical user interface with method and apparatus for interfacing to remote devices
An intuitive graphical user interface is based upon a geographic map structure, and includes a system for controlling remote external electronic devices. In the...
US-6,020,765 Frequency difference detector for use with an NRZ signal
A frequency difference detector includes a pulse generator that receives an NRZ signal and a reference signal and provides data pulses having first edges based...
US-6,018,983 Method and apparatus for matching refrigerants
Method and apparatus for freon and other refrigerant matching, particularly for servicing of air conditioning systems for automotive applications. The matching...
US-D419,913 Plant flat
US-D419,832 Knife holder
US-D419,788 Wicker and wrought iron chair
US-D419,787 Wicker and wrought iron chair
US-6,018,799 Method, apparatus and computer program product for optimizing registers in a stack using a register allocator
Apparatus, methods and computer program products are disclosed that enable a compiler to generate efficient code to access stack registers on a register stack....
US-6,018,752 Microprocessor for performing unsigned operations with signed instructions
A microprocessor operable to transform unsigned data to a signed format so that the unsigned data can be processed by signed instructions. In particular, a...
US-6,018,751 Microprocessor for performing signed operations with unsigned instructions
A mechanism in a microprocessor to transform signed data to an unsigned format so that the signed data can be processed by unsigned instructions. In particular,...
US-6,018,748 Dynamic linkable labels in a network browser page
In a computer network where remote user stations retrieve information from other sites in the network, a method and apparatus for creating and displaying dynamic...
US-6,018,724 Method and apparatus for authenticating on-line transaction data
The present invention comprises a method and apparatus for authenticating data related to on-line transactions. The invention utilizes a user-customized...
US-6,018,628 Method of implementing parameterized types to be compatible with existing unparameterized libraries
A method and apparatus for generating code using parameterized classes which is compatible with an existing class library that was previously generated using...
US-6,018,622 Method for reducing circuit area by grouping compatible storage devices
In a control block design methodology, a control block is designed, synthesized, and laid out. The control block includes one or more storage devices, such as...
US-6,018,450 Output driver with overshoot and undershoot protection
A output driving circuit having an output driving element, an overshoot protection mechanism, and an undershoot protection mechanism. When the overshoot...
US-6,018,353 Three-dimensional graphics accelerator with an improved vertex buffer for more efficient vertex processing
A vertex accumulation buffer for improved three-dimensional graphical processing is disclosed. The accumulation buffer may include two individual buffers...
US-6,018,342 Automatically generated content-based history mechanism
A history mechanism is provided in which user data, which represents signals generated by a user, are stored for subsequent recall and regeneration in a history...
US-6,018,254 Non-blocking delayed clocking system for domino logic
A non-blocking multiple-phase clocking system for use with domino-type dynamic logic provides clock phases with overlapping evaluation phases to a circuit...
US-D419,558 Radio
US-6,016,532 Method for handling data cache misses using help instructions
A microprocessor is configured to generate help instructions in response to a data cache miss. The help instructions flow through the instruction processing...
US-6,016,500 Leasing for failure detection
A system for using a lease to detect a failure and to perform failure recovery is provided. In using this system, a client requests a lease from a server to...
US-6,016,489 Method and apparatus for constructing stable iterators in a shared data collection
In a distributed object system, a stable object iterator provides a list of all persistent objects within a collection of objects. A plurality of iterators are...
US-6,016,310 Trunking support in a high performance network device
A method and apparatus for providing trunking support in a network device is provided. According to one aspect of the present invention, a network device...
US-6,016,149 Lighting unit for a three-dimensional graphics accelerator with improved processing of multiple light sources
A lighting unit for improved processing of multiple light sources. The lighting unit includes an input buffer for receiving one or more attributes corresponding...
US-6,016,082 Low phase noise LC oscillator for microprocessor clock distribution
A microprocessor includes an on-chip low phase noise CMOS LC capacitance oscillator. The LC oscillator is relatively insensitive to power supply fluctuations. In...
US-6,014,762 Method and apparatus for scan test of SRAM for microprocessor without full scan capability
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in...
US-6,014,752 Method and apparatus for fully controllable integrated circuit internal clock
A clock generation and control circuit to debug an integrated circuit includes a multiplexer connected to a set of input lines that carry a set of clock signals....
US-6,014,738 Method for computing a difference in a digital processing system
According to a presently preferred embodiment of the present invention, a method for processing a incoming signal comprising the steps of selecting from a first...
US-6,014,723 Processor with accelerated array access bounds checking
An array boundary checking apparatus is configured to verify that a referenced element of an information array is within a maximum array size boundary value and...
US-6,014,710 System and method for message transmission between network nodes using remote wires
A first computer sends a sequence of messages to a second computer using remote write operations to directly store each message in a corresponding memory...
US-6,014,669 Highly-available distributed cluster configuration database
The cluster configuration database is a distributed configuration database wherein a consistent copy of the configuration database is maintained on each active...
US-6,014,660 Method and apparatus for client-sensitive name resolution using DNS
A method and apparatus for performing client-sensitive DNS translations includes the steps of receiving a translation request by a DNS server. The DNS server...
US-6,014,514 System for generating and graphically displaying call stack information for processing elements in a parallel...
A system for generating a "where graph" for a parallel processing system comprising a parallel processing array controlled by a control processor. The processing...
US-6,014,380 Mechanism for packet field replacement in a multi-layer distributed network element
A multi-layer distributed network element for relaying packets according to known routing protocols. A distributed architecture of multiple subsystems delivers...
US-6,014,338 Single ended read scheme with global bitline of multi-port register file
A read system for a multi-ported register file includes a segmented bit line coupled to a global bit line. Each local bit line segment is coupled to a sub-set of...
US-6,014,144 Rapid computation of local eye vectors in a fixed point lighting unit
A rapid method for calculating a local eye vector in a fixed point lighting unit. For a given triangle primitive which is to be projected into a given viewport...
US-6,012,116 Apparatus and method for controlling data, address, and enable buses within a microprocessor
A CPU includes a common bus, a bus interface unit (BIU), and a plurality of module units. The BIU includes a decode stage, an arbitration stage, and a control...
US-6,011,689 Computer component cooling fan closure device and method thereof
Disclosed is a system for assisting in preventing over heating of the internal electrical components of a computer in the event of a failure of one of the...
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