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Bus interface unit having selectively enabled buffers
A computer system includes a bus interface with a plurality of data buffers. Each data buffer is clocked by an individual clock signal. To reduce the power...
Method for increasing the speed of data processing in a computer system
Method for increasing data-processing speed in computer systems containing at least one microprocessor, a memory device, and a so-called cache connected to the...
Translation look aside buffer having separate RAM arrays which are
accessable with separate enable signals
A unified array access for two logically different arrays is provided. The first array includes CAM cells arranged in n rows and x columns. At least one CAM cell...
Tooltips on webpages
A method and apparatus that allows a Web page designer to specify tooltips for his Web page. Tooltips are text areas that display automatically when the user...
Method and apparatus for improving compiler performance during
subsequent compilations of a source program
Apparatus, methods, and computer program products are disclosed for improving the performance of subsequent compilations of a source program. The initial...
Mechanism for coalescing non-cacheable stores
Data is collected from multiple data packets for group transfer on a data path so as to maximize utilization of the data path. A particularly suitable data path...
Eyetracked alert messages
User messages are automatically positioned on a display at a location at which a user's gaze is directed as indicated by an eyetracker. When a user has read the...
Verification system for simulator
An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between...
Controlled phase noise generation method for enhanced testability of
clock and data generator and recovery circuits
A transmitter/receiver chip includes circuitry for testing the bit error rate of the chip. A controlled amount of noise is introduced to the chip to vary a...
Non-inclusive cache system using pipelined snoop bus
A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of...
Look-up switch accelerator and method of operating same
A look-up switch accelerator which includes an associative memory for storing information associated with one or more look-up switch statements. For each look-up...
System and process for providing improved database interfacing using
A system and a process for providing improved interfacing to a data source storing a plurality of data using query objects are described. The data source...
Altitude sparse aircraft display
A system, method, apparatus, and computer program product for avoiding aircraft collisions with stationary obstacles. The aircraft is provided with a simplified...
Encoding machine-specific optimization in generic byte code by using
local variables as pseudo-registers
A first computer system (34) compiles a source program into machine code for a register-oriented microprocessor, optimizing the global allocation of...
System and method for pre-verification of stack usage in bytecode
The present invention provides a verifier for use in conjunction with programs utilizing data type specific bytecodes for verifying the proper operation of the...
Method for efficient implementation of multi-ported logic FIFO
structures in a processor
A system and method for efficient implementation of a multi-port logic first-in, first-out ("FIFO") structure or particular utility in high clock speed...
Method of drying konjak in producing dried seasoned konjak
A method of drying konjak slices in producing seasoned dried konjak slices is provided which method allows for reducing the drying time while at the same time...
Apparatus and method for simulating multiple nodes on a single machine
The present invention pertains to a system and method for simulating multiple clusters of independent computer nodes in a single machine. A cluster contains one...
Network interface circuit with replacement circuitry and method for
segregating memory in an address...
A circuit and method for segregating address entries of memory, internal to an address translation unit, into locked and unlocked regions. The locked region is a...
Reducing bandwidth and areas needed for non-inclusive memory hierarchy
by using dual tags
An apparatus and method for optimizing a non-inclusive hierarchical cache memory system that includes a first and second cache for storing information. The first and...
Method and apparatus for assignment of IP addresses
A preferred embodiment of the present invention includes a method and apparatus for allocating and using IP addresses in a network of client systems. More...
Apparatus for directing a parallel processing computing device to form
an absolute value of a signed value
In the present invention, a method for directing parallel processing computing device to perform the operation of setting a signed value of N bits to an absolute...
Document editor for linear and space efficient representation of
A computer system and method edits a hierarchical document that has starttags and endtags and leaf contents between ones of the starttags and endtags. The...
Compatibility checking between instruments, operations and protocols in
The present invention provides a modular infrastructure for electronic commerce that allows electronic financial instruments to work with a variety of different...
System for automated electromigration verification
An automated apparatus detects electromigration violations in an integrated circuit design. Starting from the lowest hierarchy of the design so far completed,...
An arbiter is disclosed for determining a sequence of signals indicative of events occurring variously on at least two input connections. The arbiter includes a...
Tunable threshold SOI device using isolated well structure for back gate
To reduce threshold levels in fully depleted SOI devices having back gate wells, the channel regions of the devices are formed of an intrinsic or ...
Primer composition and curable composition
A curable dental adhesive composition of the type including polymerizable monomer and polymerization initiator may be easily prepared and applied to a tooth...
Surfboard having embedded reinforcing mesh
A surfboard includes a board and a plate secured to the bottom of the board and formed by a foamable material. A reinforcing mesh is embedded in the plate and...
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Method and apparatus for high availability and caching data storage
A method and apparatus for high availability and caching data storage devices. According to a preferred embodiment of the invention, there is provided an...
Method to activate unregistered systems in a distributed multiserver
The present invention includes a method and apparatus for registering devices in a computer network. Initially, for an unregistered device, the network...
System and method for executing verifiable programs with facility for
using non-verifiable programs from...
A computer system includes a program executer that executes verifiable architecture neutral programs and a class loader that prohibits the loading and execution...
Method and system for efficient organization of selectable elements on a
graphical user interface
In a preferred embodiment, the present invention provides a method and system for organizing selectable elements on a graphical user interface (GUI). Initially,...
Voltage regulation method for attenuating inductance-induced on-chip
An active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during...
High voltage input buffer circuit using low voltage transistors
An input buffer circuit implemented with low voltage transistors, that is capable of receiving and recognizing input logic signals having higher voltage levels...
Using asynchronous FIFO control rings for synchronous systems
A system for distributing clock signals to multiple locations on a chip with minimal skew is disclosed. A series of FIFO control structures, connected in a ring...
Multi-stack-caching memory architecture
The present invention provides a memory system that caches method frames using multiple stack cache management units to provide access to multiple portions of...
System and method for generating trusted, architecture specific,
compiled versions of architecture neutral programs
A distributed computer system has a program compiling computer and a program executing computer. The program compiling computer is operated by a compiling party...
Disk drive bracket
A bracket having two parallel sides and an interconnecting crosspiece is attached to a disk drive or similar peripheral with the sides of the bracket extending...
High-performance band combine function
A high-performance band combine function to transform a source image of n bands to a destination image of m bands. A source image vector is multiplied with a...
Image for a computer display
Arbitration logic using a four-phase signaling protocol for control of a
counterflow pipeline processor
A counterflow pipeline is provided which includes an instruction pipeline having a plurality of stages for transmitting instruction packets in a first direction...
Non-quick instruction accelerator including instruction identifier and
data set storage and method of...
An instruction accelerator which includes a processor and an associative memory. The processor is coupled to receive a stream of instructions and a corresponding...
Apparatus and method for sharing a unified memory bus between external
cache memory and primary memory
A computer system includes a central processing unit with an internal memory controller. The internal memory controller interacts with an external cache and a...
System for maintaining strongly sequentially ordered packet flow in a
ring network system with busy and failed...
A system for maintaining reliable packet distribution in a ring network with support for strongly ordered, nonidempotent commands. Each consumer node on the...