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Patent # Description
US-6,088,758 Method and apparatus for distributing data in a digital data processor with distributed memory
A digital data processing system and method with shared, distributed memory transfers data between corresponding data sets within memory. The digital data...
US-6,088,356 System and method for a multi-layer network element
A multi-layer network element for forwarding received packets from an input port to one or more output ports. The packet is examined to look for first and second...
US-6,088,034 Decompression of surface normals in three-dimensional graphics data
Three-dimensional compressed geometry is decompressed with a unit having an input FIFO receiving compressed data bits and outputting to an input block state...
US-6,087,892 Target Ion/Ioff threshold tuning circuit and method
To compensate for process, activity and environmental variations in a semiconductor device, a ratio of a transistor on-current to a transistor off-current within...
US-6,086,623 Method and implementation for intercepting and processing system calls in programmed digital computer to...
A current operating system such as Solaris.RTM. X86 is adapted to run a user program such as a Common Object File Format (COFF) executable program which was...
US-6,085,462 Molded plant tray
A molded plant tray is provided in the form of a unitary molded plastic member formed of relatively light foamed plastic and having downwardly extending tapered...
US-D428,180 Outdoor luminaire
US-6,085,343 Method for concurrent testing of on-chip circuitry and timing counters
A testing method in which the stages in a multi-stage counter chain are tested sequentially. A counter chain is composed of two or more stages with the carry-out...
US-6,085,316 Layered counterflow pipeline processor with anticipatory control
A layered counterflow pipeline structure is described in which sub-tasks performed at each stage in a counterflow pipeline processor are separated into different...
US-6,085,305 Apparatus for precise architectural update in an out-of-order processor
A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor...
US-6,085,244 Dynamic test update in a remote computer monitoring system
A remote monitoring system automatically communicates system diagnostic information from a monitored computer system to a remote service center at regular...
US-6,085,228 Methods and apparatus for a property editing mechanism for a network computer environment
A system allows an administrator to edit, from a client, property files that reside on a server. The client issues a request to the server for property...
US-6,085,207 Method of performing signed operations with unsigned instructions in a microprocessor
A method for controlling a microprocessor to transform data from a signed format to an unsigned format so that the data can be processed by unsigned ...
US-6,085,198 Integrated three-tier application framework with automated class and table generation
An integrated three-tier application framework with automated class and database table generation. Schema information in the form of metadata structures is used...
US-6,085,191 System and method for providing database access control in a secure distributed network
An access control database has access control objects that collectively store information that specifies access rights by users to specified sets of the managed...
US-6,085,035 Method and apparatus for efficient operations on primary type values without static overloading
Apparatus, methods, and computer program products are disclosed for providing optimized access to pointer or externally-tagged primitive type data-values. The...
US-6,085,033 Method for determining bit element values for driver impedance control
A method for determining bit element values for an impedance control circuit is provided which controls the output impedance of drivers which are coupled to the...
US-6,084,452 Clock duty cycle control technique
An apparatus adjusts the duty cycle of a single-ended clock signal. The single-ended clock signal oscillates between first and second voltages. The apparatus...
US-6,083,277 Filtering an object interface definition to determine services needed and provided
A distributed object application builder apparatus filters an object definition to determine the information needed (plugs) and provided (sockets) by an object....
US-6,082,129 Sorption refrigeration appliance
A combination heating and cooling apparatus which comprises a compartment into which an item to be heated or cooled may be placed; an electromagnetic wave...
US-6,081,913 Method for ensuring mutual exclusivity of selected signals during application of test patterns
A method for controlling a gating circuit of an electronic system incorporating a scan architecture complying with IEEE Standard 1149.1 such that the gating...
US-6,081,873 In-line bank conflict detection and resolution in a multi-ported non-blocking cache
A data cache unit associated with a processor, the data cache unit including a multi-ported non-blocking cache receiving a data access request from a lower level...
US-6,081,844 Point-to-point interconnect communications utility
An interconnect controller for use in an arbitrary topology collection of nodes in a network suitable for use for both data sharing and distributed computing....
US-6,081,767 Method and device for determining the amount of undissolved gas in a hydraulic system
The invention provides a method for determining the amount of undissolved gas present in a hydraulic system by supplying hydraulic medium thereto under...
US-6,081,522 System and method for a multi-layer network element
A multi-layer network element for forwarding received packets from an input port to one or more output ports. The packet is examined to look for different types...
US-6,081,512 Spanning tree support in a high performance network device
A method and apparatus for providing spanning tree support are provided. According to one aspect of the present invention, a network device includes two or more...
US-6,081,143 Frequency comparison and generation in an integrated processor
An integrated processor includes a microprocessor core and a bus interface unit. The integrated processor receives a reference clock signal and an external clock...
US-6,081,028 Thermal management enhancements for cavity packages
A thermal conducting material for providing lateral thermal conduction across a surface of an integrated circuit and for enhancing thermal dissipation from the...
US-6,081,022 Clock distribution network with efficient shielding
An interconnect structure includes in a first layer a clock line and a ground line running substantially parallel to the clock line, and a plurality of...
US-D427,391 Flashing dog bone chew toy
US-D427,390 Hydrant chew toy
US-6,079,024 Bus interface unit having selectively enabled buffers
A computer system includes a bus interface with a plurality of data buffers. Each data buffer is clocked by an individual clock signal. To reduce the power...
US-6,078,996 Method for increasing the speed of data processing in a computer system
Method for increasing data-processing speed in computer systems containing at least one microprocessor, a memory device, and a so-called cache connected to the...
US-6,078,987 Translation look aside buffer having separate RAM arrays which are accessable with separate enable signals
A unified array access for two logically different arrays is provided. The first array includes CAM cells arranged in n rows and x columns. At least one CAM cell...
US-6,078,935 Tooltips on webpages
A method and apparatus that allows a Web page designer to specify tooltips for his Web page. Tooltips are text areas that display automatically when the user...
US-6,078,744 Method and apparatus for improving compiler performance during subsequent compilations of a source program
Apparatus, methods, and computer program products are disclosed for improving the performance of subsequent compilations of a source program. The initial...
US-6,078,587 Mechanism for coalescing non-cacheable stores
Data is collected from multiple data packets for group transfer on a data path so as to maximize utilization of the data path. A particularly suitable data path...
US-6,078,310 Eyetracked alert messages
User messages are automatically positioned on a display at a location at which a user's gaze is directed as indicated by an eyetracker. When a user has read the...
US-6,077,304 Verification system for simulator
An electronic circuit verification system and method includes an HDL circuit simulator and a circuit simulation verifier that pass control back and forth between...
US-6,076,175 Controlled phase noise generation method for enhanced testability of clock and data generator and recovery circuits
A transmitter/receiver chip includes circuitry for testing the bit error rate of the chip. A controlled amount of noise is introduced to the chip to vary a...
US-6,076,147 Non-inclusive cache system using pipelined snoop bus
A non-inclusive cache system includes an external cache and a plurality of on-chip caches each having a set of tags associated therewith, with at least one of...
US-6,076,141 Look-up switch accelerator and method of operating same
A look-up switch accelerator which includes an associative memory for storing information associated with one or more look-up switch statements. For each look-up...
US-6,076,092 System and process for providing improved database interfacing using query objects
A system and a process for providing improved interfacing to a data source storing a plurality of data using query objects are described. The data source...
US-6,076,042 Altitude sparse aircraft display
A system, method, apparatus, and computer program product for avoiding aircraft collisions with stationary obstacles. The aircraft is provided with a simplified...
US-6,075,942 Encoding machine-specific optimization in generic byte code by using local variables as pseudo-registers
A first computer system (34) compiles a source program into machine code for a register-oriented microprocessor, optimizing the global allocation of...
US-6,075,940 System and method for pre-verification of stack usage in bytecode program loops
The present invention provides a verifier for use in conjunction with programs utilizing data type specific bytecodes for verifying the proper operation of the...
US-6,075,931 Method for efficient implementation of multi-ported logic FIFO structures in a processor
A system and method for efficient implementation of a multi-port logic first-in, first-out ("FIFO") structure or particular utility in high clock speed...
US-6,074,681 Method of drying konjak in producing dried seasoned konjak
A method of drying konjak slices in producing seasoned dried konjak slices is provided which method allows for reducing the drying time while at the same time...
US-6,074,427 Apparatus and method for simulating multiple nodes on a single machine
The present invention pertains to a system and method for simulating multiple clusters of independent computer nodes in a single machine. A cluster contains one...
US-6,073,224 Network interface circuit with replacement circuitry and method for segregating memory in an address...
A circuit and method for segregating address entries of memory, internal to an address translation unit, into locked and unlocked regions. The locked region is a...
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