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Patent # Description
US-6,122,709 Cache with reduced tag information storage
A cache memory system including a cache memory having a plurality of cache lines. An index portion of a tag array includes an n-bit pointer entry for every cache...
US-6,121,871 Apparatus and method for comparing digital words using a last bit detection operation
A circuit for comparing two digital words has a set of bit compare circuits that generate a set of compare signals. Each bit compare circuit receives a first bit...
US-6,121,807 Single phase edge-triggered dual-rail dynamic flip-flop
A single phase edge-triggered dual-rail dynamic flip-flop circuit for use with dynamic logic gates includes an input stage, precharge stage and buffer. The input...
US-6,121,666 Split gate oxide asymmetric MOS devices
A method for making an asymmetric MOS device having a notched gate oxide is disclosed herein. Such MOS devices have a region of a gate oxide adjacent to either...
US-6,119,722 Pilot operated pressure valve
A pilot operated pressure valve which limits the rate of pressure rise and substantially eliminates excessive system pressure spikes, the valve including an...
US-6,119,234 Method and apparatus for client-host communication over a computer network
A method and apparatus are provided for dynamically configuring authorized clients with the address of a protected host and the key and address of an ...
US-6,119,232 Flexible mounting and unmounting of user removable media
A computer implemented method and apparatus for mounting a user removable media in a computer system includes acquiring a media identifier input and a function...
US-6,119,206 Design of tags for lookup of non-volatile registers
Stack tracebacks are performed in debugging and exception handling routines, and involve providing the values of non-volatile registers at the time of entry into...
US-6,119,205 Speculative cache line write backs to avoid hotspots
A cache system including a data cache memory comprising a plurality of cache lines. A tag store has an entry representing each line in the cache memory where...
US-6,119,196 System having multiple arbitrating levels for arbitrating access to a shared memory by network ports operating...
A method and apparatus for managing a buffer memory in a packet switch that is shared between multiple ports in a network system. The apparatus comprises a...
US-6,119,157 Protocol for exchanging configuration data in a computer network
Methods and apparatus are disclosed for providing a data framework and associated client/server protocol for storing and exchanging data among computers in a...
US-6,119,129 Multi-threaded journaling in a configuration database
A method and system for creating and maintaining a journal of transactions directed to a configuration database is disclosed. A multi-threaded journaling method...
US-6,118,760 Management of entries in a network element forwarding memory
The invention generally provides for a network element and methods in the network element for allowing a matching entry in a forwarding memory to be found in a...
US-6,118,472 Method and apparatus for seamless connectivity of wide-band networks and narrow-band networks
An apparatus for seamless connectivity between a narrow-band network like the Internet and an interactive TV wide-band network and methods of operating the same...
US-6,118,401 Aircraft ground collision avoidance system and method
A system and method for avoiding collision between objects and wingtips of an aircraft when the aircraft is on the ground includes mounting detecting devices...
US-6,117,181 Synchronization mechanism for distributed hardware simulation
The synchronization state of each of a number of concurrently executing tests which interacts with a particular circuit simulation of one or more circuit...
US-6,116,039 Cooling apparatus having integrated sorber-evaporator structure
An apparatus for cooling an electrical component is disclosed which comprises a sorber containing a sorbent; a condenser in fluid communication with the sorber;...
US-6,115,811 Digital data process system including efficient arrangement to support branching within trap shadows
A digital computer includes an efficient mechanism by which an exception handler can traverse the instruction stream in a reverse direction to identify the...
US-6,115,810 Bi-level branch target prediction scheme with mux select prediction
One embodiment of the present invention provides a system for predicting an address of an instruction following a branch instruction in a computer instruction...
US-6,115,802 Efficient hash table for use in multi-threaded environments
A lockless-lookup hash table for use in a multi-threaded processing system has a memory whose storage locations hold elements. Each memory location is uniquely...
US-6,115,782 Method and apparatus for locating nodes in a carded heap using a card marking structure and a node advance value
Apparatus, methods, systems, and computer program products are disclosed that locate a modified pointer value in a carded heap memory. A plurality of nodes is...
US-6,115,756 Electro-optically connected multiprocessor and multiring configuration for dynamically allocating time
A computer system employs a hierarchical ring structure for communication. Computer system elements are configured into modules with ring interface hardware, and...
US-6,115,752 System and method for server selection for mirrored sites
The present invention is a system and method for providing server selection for mirrored sites. In one embodiment, a user requests an address via a local name...
US-6,115,715 Transaction management in a configuration database
A method and system are disclosed for updating and managing a configuration database used to store configuration and user data in a computer network having...
US-6,115,378 Multi-layer distributed network element
A distributed multi-layer network element delivering Layer 2 (data link layer) wire-speed performance within and across subnetworks, allowing queuing decisions...
US-6,115,047 Method and apparatus for implementing efficient floating point Z-buffering
A method for handling Z-values in accordance with the present invention. The Z-values correspond to vertices of a given primitive being processed within a...
US-6,112,282 Apparatus for atomic locking-accessing-unlocking of a shared resource
An atomic instruction is executed without the use of a dedicated atomic unit. A store instruction is transmitted from a front-end of one of a plurality of...
US-6,112,025 System and method for dynamic program linking
In a system for dynamically linking a compiled procedure to referenced object components during execution of the compiled procedure, a native code loader loads...
US-6,111,436 Measurement of signal propagation delay using arbiters
Arbiter circuits placed between two signal path segments on a semiconductor chip to measure the difference in propagation delay between those paths at their...
US-6,110,783 Method for forming a notched gate oxide asymmetric MOS device
A method for making an asymmetric MOS device having a notched gate oxide wherein a region of the gate oxide adjacent to either the source or drain is thinner...
US-6,110,221 Repeater blocks adjacent clusters of circuits
The present invention organizes the circuits on a VLSI chip into clusters. A number of channels exist in-between the clusters. Blocks of repeaters are used in a...
US-6,109,484 Dropping container
A dropping container includes a cylindrical body, a dropping portion having a pressure valve for closing an opening in the dropping container body such that it...
US-D430,160 Device housing
US-D430,063 Three-wheeled scooter
US-6,108,768 Reissue logic for individually reissuing instructions trapped in a multiissue stack based computing system
An execution unit that executes multiple instructions as a single instruction group during a single processing cycle is provided. The execution unit handles...
US-6,108,767 Method, apparatus and computer program product for selecting a predictor to minimize exception traps from a...
Apparatus, methods, and computer program products are disclosed that improve the operation of a computer that uses a top-of-stack cache by reducing the number of...
US-6,108,754 Thread-local synchronization construct cache
A method and apparatus for synchronizing objects with threads is described. To find a specific synchronization construct that is to be used to synchronize a...
US-6,108,744 Software interrupt mechanism
An interrupt mechanism for an operating system is portable to different data processing hardware. The interrupt mechanism includes a software interrupt...
US-6,108,699 System and method for modifying membership in a clustered distributed computer system and updating system...
Multiple nodes can concurrently gain membership in a cluster of nodes of a distributed computer system by broadcasting reconfiguration messages to all nodes of...
US-6,108,695 Method and apparatus for providing analog output and managing channels on a multiple channel digital media server
A method and apparatus for providing analog output and managing channels on a multiple channel digital media server are provided. A mapping is established...
US-6,108,688 System for reminding a sender of an email if recipient of the email does not respond by a selected time set by...
A system for warning the sender of e-mail messages if the messages are not received is described. The system permits the sender of a message to designate whether...
US-6,107,946 High speed serial link for fully duplexed data communication
A system for converting between parallel data and serial data is described. In the system 10, individual bits of the parallel data 12 are latched into individual...
US-6,105,736 Disc brake and anti-squeal shim therefor
An anti-squeal shim comprises a metal plate and a compound layer applied only to one face of the metal plate. The compound includes a nonmetal fiber other than...
US-6,105,110 Circuit and method for replacement of address translations
A circuit used to control the modification of content within memory implemented within an address translation unit. This memory includes a plurality of entries...
US-6,105,040 Method and apparatus for managing stored objects
In accordance with the present invention a method is provided for managing objects during a garbage collection operation. The process comprises the steps of...
US-6,105,012 Security system and method for financial institution server and client web browser
The financial transaction processing system includes at least one financial server connected through a public network to a number of users associated with client...
US-6,104,695 Repair TTL computation and correction mechanism to perform localized repairs in a multicast data distribution...
Determination of a Time To Live ("TTL") hop count for repair data units transmitted from a repair head to a standard destination device in a communications...
US-6,104,397 Method and system for generating improved progress indicators
A method and system for generating improved command progress indicator including the steps of establishing at a location of a display at least one...
US-6,104,258 System and method for edge termination of parallel conductive planes in an electrical interconnecting apparatus
A system and method are presented for stabilizing the electrical impedance of an electrical interconnecting apparatus including a pair of parallel planar...
US-6,104,215 Signal detector with improved noise immunity
A method for processing a signal transitioning from a high state to a low state is described, comprising the steps of detecting a transition of the signal from a...
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