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Patent # Description
US-6,182,110 Network tasks scheduling
Method and apparatus for efficiently scheduling tasks on a network. A user may schedule node-specific tasks across the network without specifying particular...
US-6,182,083 Method and system for multi-entry and multi-template matching in a database
A database system wherein one or more entry databases store a plurality of entries. Each entry is of a given type that defines the fields of the entry. Each...
US-6,182,063 Method and apparatus for cascaded indexing and retrieval
Systems and methods consistent with the present invention respond to queries of stored information by receiving a query identifying desired information;...
US-6,182,025 Remote terminal emulator
A remote terminal emulator (RTE) is provided in which substantially all of the time elapsing during an emulated use of a computer system under test is...
US-6,181,713 Selectable depacketizer architecture
A scheme is provided that permits the use of a selectable depacketization module to depacketize data streams. An RTP session manager is responsible for receiving...
US-6,179,763 Box making machines and method of retrofitting
An existing box-making machine is retrofitted by first removing the pull rolls and impression cylinder and other associated parts and cross-ties. However, the...
US-6,179,698 Self-aligning tool for hands-free cross-sectioning of an integrated circuit
A tool is provided for cross-sectioning an integrated circuit in a hands-free mode of operation. The tool comprises an enclosure or cage having a passageway...
US-6,179,382 Yarn having wicker appearance and articles made therefrom
A stackable arm chair is constructed from the combination of a frame which supports woven material to form the chair's seat, back and side arm portions. Openings...
US-6,178,533 Method and system for design verification
The present invention pertains to a dynamic process for generating biased pseudo-random test patterns for the functional verification of a microprocessor having...
US-6,175,898 Method for prefetching data using a micro-TLB
A memory cache method and apparatus with two memory execution pipelines, each having a translation lookaside buffer (TLB). Memory instructions are executed in...
US-6,175,887 Deterministic arbitration of a serial bus using arbitration addresses
An apparatus, system, and method for arbitrating for a serial bus in an efficient manner. An arbitration phase includes master devices asserting respective...
US-6,175,837 Object-relational mapping toll that processes views
An object-relational mapping tool that can process views is provided. In processing views, the object-relational mapping tool identifies the dependency...
US-6,175,364 Framework and method for interfacing a GUI, container with a GUI component
Methods, software and data structures for installing a component in a container suitable for display on a display screen as part of a graphical user interface...
US-D436,289 Handle for kitchen tooling
US-6,173,442 Busy-wait-free synchronization
An object structure's header (40) allocates a two-bit synchronization-state field (42) solely to monitor data for implementing synchronization on that object....
US-6,173,416 System and method for detecting errors using CPU signature
A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a...
US-6,173,413 Mechanism for maintaining constant permissions for multiple instances of a device within a cluster
A cluster implements a virtual disk system that provides each node of the cluster access to each storage device of the cluster. The virtual disk system provides...
US-6,173,400 Methods and systems for establishing a shared secret using an authentication token
A method and system for establishing a shared secret between a plurality of devices using an authentication token. An authentication token is used to establish a...
US-6,173,353 Method and apparatus for dual bus memory transactions
During burst write transactions, a memory accepts data over an address bus after an address has been received. In order to accept data over the address bus, the...
US-6,173,351 Multi-processor system bridge
A bridge for a multi-processor system provides interfaces to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A...
US-6,173,290 Method and apparatus for coupling object state and behavior in a database management system
A method and apparatus for coupling object state and behavior in a DBMS is provided such that an object's class definition, behavior information, and state...
US-6,173,283 Method, apparatus, and product for linking a user to records of a database
In accordance with the present invention a method and system for linking a user to a data record in a directory comprises the steps, performed by one or more...
US-6,172,879 BGA pin isolation and signal routing process
A method for isolating a pin of a ball grid array (BGA) device mounted on a printed circuit board, and routing the signal carried by the isolated pin to an...
US-6,171,135 Lamp base
A lamp base includes a base body, a lamp socket fixed under the base body, a housing protecting the base body and the lamp socket, and a cap closing up the...
US-6,170,620 Disc brake and anti-squeal shim therefor
An anti-squeal shim comprises a metal plate and a compound layer applied to at least one side of the metal plate. The compound includes a nonmetal fiber other...
US-6,170,068 System and method for preserving the state of a device across a reset event
A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a...
US-6,170,050 Length decoder for variable length data
A length decoder that rapidly calculates the group lengths of groups of variable length data words is provided. In accordance with one embodiment, a length...
US-6,170,018 Remote procedure calling using an existing descriptor mechanism
Doors are implemented in an existing operating system by using a novel adaptation of existing data structures and procedures which represent and control data...
US-6,169,911 Graphical user interface for a portable telephone
A portable telephone provides a graphical user interface (GUI) using a high-resolution display. The GUI provides a Universal Mailbox for storing both electronic...
US-6,169,554 Clip testing unit for a three-dimensional graphics accelerator
A clip testing unit within a graphics accelerator for comparing a value of a given homogeneous coordinate of a vertex position of a polygon relative to a...
US-6,169,422 Apparatus and methods for high throughput self-timed domino circuits
Asynchronous circuitry provides a domino circuit having short cycle times and zero overhead latency. The control circuit of a datapath circuit may utilize a...
US-6,167,568 Method and apparatus for implementing electronic software distribution
An embodiment consistent with the present invention includes a method and apparatus for performing software distribution of a software product electronically....
US-6,167,535 Object heap analysis techniques for discovering memory leaks and other run-time information
Techniques for analyzing object-oriented computer programs are provided. A snapshot of the objects that are active at a specific point in time during execution...
US-6,167,522 Method and apparatus for providing security for servers executing application programs received via a network
A method and apparatus for providing security to a server running an application program received over a network is provided. The application program, along with...
US-6,167,504 Method, apparatus and computer program product for processing stack related exception traps
Apparatus, methods, and computer program products are disclosed that improve the operation of a computer that uses a top-of-stack cache by reducing the number of...
US-6,167,488 Stack caching circuit with overflow/underflow unit
The present invention provides a stack management unit including a stack cache to accelerate data retrieval from a stack and data storage into the stack. In one...
US-6,167,477 Computer system bridge employing a resource control mechanism with programmable registers to control resource...
A bridge for a computer system comprising at least a first processing set and a second processing set each connected to the bridge via an I/O bus. A resource...
US-6,167,458 Transport independent invocation and servant interfaces that permit both typecode interpreted and compiled...
Data structures, methods, and devices for facilitating servant invocation in a distributed client-server based object oriented operating system are disclosed. In...
US-6,167,424 Method and apparatus for concurrent thread synchronization
Methods and apparatus for locking and unlocking objects using synchronized threads are disclosed. According to one aspect of the present invention, a ...
US-6,167,402 High performance message store
A product and method are disclosed for creating an efficient message store and delivery system is provided. A message store having an index directory, index...
US-6,166,438 Ultrathin electronics using stacked layers and interconnect vias
An integrated circuit and associated method for reducing total signal propagation delay as well as power consumption and thermal dissipation. The integrated...
US-6,164,840 Ensuring consistency of an instruction cache with a store cache check and an execution blocking flush...
A method of ensuring instruction cache consistency in a processor includes executing a flush instruction whenever a program executed by the processor stores data...
US-6,164,517 Seamless, ring-shaped brazing material and method for producing same
The seamless, ring-shaped brazing material comprises a brazing metal and a flux uniformly dispersed in the brazing metal for brazing nonferrous metal members and...
US-6,164,096 Housing construction for rotating dial combination padlocks
By providing a removable cover assembly mountable to a rotating dial of a central housing of a padlock, a padlock construction is attained which is visually...
US-6,163,866 System level IC testing arrangement and method
A method and apparatus for testing an integrated circuit in a system level environment such that the integrated circuit to be tested is wired into a system or...
US-6,163,856 Method and apparatus for file system disaster recovery
A file disaster recovery system that employs geographical replication of data from a local site to remote site in a such a manner that file requests from clients...
US-6,163,837 Writing of instruction results produced by instruction execution circuits to result destinations
Two instruction executions circuits C1 and C2, possibly pipelined, share a write port to write instruction results to their destinations. When both circuits have...
US-6,163,806 System and method for transparent, global access to physical devices on a computer cluster
A system and method are disclosed that provides transparent, global access to devices on a computer cluster. The present system generates unique device type...
US-6,163,778 Probabilistic web link viability marker and web page ratings
Hypertext information links are typically contained in documents accessible by networks. Data is gathered regarding the results of attempted access to documents...
US-6,163,192 Negative pulse edge triggered flip-flop
A negative edge triggered flip-flop generates an output pulse in response to a negative edge of a clock signal. A first set of nodes receives data input signals,...
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