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Patent # Description
US-6,456,281 Method and apparatus for selective enabling of Addressable display elements
A method and apparatus for driving a plurality of addressable elements consist of driving and selectively enabling one or more addressable elements arranged as...
US-6,456,139 Auto-detection and auto-enable of compact PCI bus pull-ups
A device for automatically varying resistance includes a comparator for comparing a control voltage to a reference voltage; a switch operatively coupled to the...
US-6,456,136 Method and apparatus for latching data within a digital system
A latching data system includes a memory element that is configured to store a data value. A latch input is coupled to the memory element, so that changes in the...
US-6,456,107 CMOS-microprocessor chip and package anti-resonance method
A method for regulating resonance in a micro-chip has been developed. The circuit includes an on-chip de-coupled capacitor that is shunted across the supply and...
US-6,453,467 Methods and apparatus for linking a program for remote execution
A linkage editor executing at a server receives instructions for packaging software components that are required for program execution at a client. The linkage...
US-6,453,463 Method and apparatus for providing finer marking granularity for fields within objects
One embodiment of the present invention provides a system that facilitates marking of objects defined within an object-oriented programming system to keep track...
US-6,453,440 System and method for detecting double-bit errors and for correcting errors due to component failures
A system for detecting and correcting errors in a data block includes a check bits generation unit which receives and encodes data to be protected. The check...
US-6,453,403 System and method for memory management using contiguous fixed-size blocks
A system and method for memory allocation from a heap comprising memory blocks of a uniform fixed size. Each memory block has a status bit. A binary status key...
US-6,453,360 High performance network interface
A high performance network interface is provided for receiving a packet from a network and transferring it to a host computer system. A header portion of a...
US-6,453,327 Method and apparatus for identifying and discarding junk electronic mail
Apparatus, methods, systems and computer program products are disclosed to provide electronic mail systems with the capability for a group of trusted users to...
US-6,452,794 Grounding computer systems
A computer system includes a chassis, electronic circuitry, a plurality of removable power supply units, and a power distribution mechanism to which the power...
US-6,452,692 Networked printer server
A print server for print jobs printed on networked printers. First, the print server receives preferences regarding a print job the user wishes to send such as...
US-6,452,585 Radio frequency tracking system
A method and apparatus is disclosed for transmitting data about an object within a defined field and using the transmitted data to generate a virtual object on...
US-6,452,574 Hood-shaped support frame for a low cost virtual reality system
Apparatus is disclosed for viewing computer generated images and for tracking the positions of the user's head and hand. One alternative of the apparatus...
US-6,452,423 Circuit for avoiding contention in one-hot or one-cold multiplexer designs
A circuit for avoiding contention in such circuits as an n-to-1 transmission gate multiplexer in a high performance microprocessor or integrated circuit utilizes...
US-6,451,953 Chain entanglement crosslinked polymers
A rigid crosslinked polymer having effective levels of chain entanglement crosslinking produced by a rapid rate polymerization procedure which comprises the...
US-6,451,873 Low VOC cationic curable lithographic printing inks
Lithographic printing ink formulations compatible with cationic catalysts containing a diluent and rheology modifying resins curable by cationic polymerization...
US-6,450,327 Paper palette for art
A paper palette for art used for mixing colors and other paints for art or arranging the point of a brush is formed by partially bundling plural pieces of paper....
US-D462,968 Bezel for computer workstation
US-6,449,754 Method of measuring the accuracy of parasitic capacitance extraction
A technique measuring accuracy of parasitic capacitance extraction defines the error in an extracted total net parasitic capacitance intended for timing analysis...
US-6,449,753 Hierarchical coupling noise analysis for submicron integrated circuit designs
An automated method of analyzing crosstalk in a digital logic integrated circuit on a digital computer is described. The method uses available software to make...
US-6,449,711 Method, apparatus, and article of manufacture for developing and executing data flow programs
Methods, systems, and articles of manufacture consistent with the present invention provide a development tool that enables computer programmers to design and...
US-6,449,700 Multiprocessing computer system employing a cluster protection mechanism
A multiprocessing system includes a plurality of nodes interconnected through a global interconnect network which supports cluster communications. An initiating...
US-6,449,648 Lease renewal service
In accordance with methods and systems consistent with the present invention, a lease manager is provided for managing leases between clients and other network...
US-6,449,641 Determining cluster membership in a distributed computer system
Cluster membership in a distributed computer system is determined by determining with which other nodes each node is in communication and distributing that...
US-6,449,626 Reduced-cost remembered-set processing in a train-algorithm-based garbage collector
A garbage collector collects a generation of a collected heap in accordance with the train algorithm. It employs remembered sets associated with respective car...
US-6,448,829 Low hold time statisized dynamic flip-flop
A low hold time flip-flop that has a dynamic input stage and a static output stage is provided. The flip-flop uses a feedback stage to maintain a value on a...
US-6,447,309 Suppressing power bus bouncing in a hot-swappable system
An apparatus for suppressing power bus bouncing in a hot-swappable system has been developed. The apparatus includes a connection module with three interior pins...
US-6,446,245 Method and apparatus for performing power routing in ASIC design
A method and apparatus for performing power routing in ASIC design. Power routing is performed after cell placement, allowing more knowledgeable placement of...
US-6,446,219 Highly available cluster message passing facility
A cluster implements a virtual disk system that provides each node of the cluster access to each storage device of the cluster. The virtual disk system provides...
US-6,446,185 Selective address translation in coherent memory replication
A multiprocessing computer system employs local and global address spaces and multiple access modes. A portion of the global memory of the multiprocessing...
US-6,446,168 Method and apparatus for dynamically switching a cache between direct-mapped and 4-way set associativity
A method of dynamically switching mapping schemes for cache includes a microprocessor, a first mapping scheme, a second mapping scheme and switching circuitry...
US-6,446,137 Remote procedure call system and method for RPC mechanism independent client and server interfaces...
A system and method allow client applications to invoke remote procedures on a server application using any of a plurality of remote procedure mechanisms, by...
US-6,446,116 Method and apparatus for dynamic loading of a transport mechanism in a multipoint data delivery system
A method and apparatus for dynamic loading of a transport mechanism is provided. A resource locator (RL) corresponding to a collaboration session is requested...
US-6,446,109 Application computing environment
A computing environment that offers a level of decentralization wherein application server code resident on a remote application server can be distributed to a...
US-6,446,104 Double precision floating point multiplier having a 32-bit booth-encoded array multiplier
A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double...
US-6,446,084 Optimizing symbol table lookups in platform-independent virtual machines
One embodiment of the present invention provides a method for increasing performance of code executing on a platform-independent virtual machine. The method...
US-6,446,070 Method and apparatus for dynamic distributed computing over a network
A homogeneous execution environment operates within a heterogeneous client-server network. A client selects a server and transmits a procedure call with...
US-6,445,640 Method and apparatus for invalidating memory array write operations
An electronic device that invalidates a memory write operation before a memory address predecode occurs. The electronic device uses several dynamic latches to...
US-6,445,391 Visible-object determination for interactive visualization
A system and method for performing visible object determination based upon a dual search of a cone hierarchy and a bounding (e.g. hull) hierarchy. Visualization...
US-6,444,022 Water based offset lithographic printing ink
A water based offset lithographic ink comprising water; a modified rosin polymer comprised of resins soluble in water regardless of the pH of the water, resin...
US-6,444,021 Water washable lithographic newspaper printing ink
A water washable lithographic newspaper ink comprising: a modified soybean oil based resin; pigment; an acid neutralizing agent; and a humectant. In addition,...
US-6,442,718 Memory module test system with reduced driver output impedance
A memory module test system with reduced driver output impedance. A test system includes a plurality of driver circuits, each of which is coupled to a...
US-6,442,670 Data processing system including a shared memory resource circuit
A data processing system comprises a plurality of nodes and a serial data bus interconnecting the nodes in series in a closed loop, for passing address and data...
US-6,442,633 Reduced transistors data switch port wherein each of a plurality of transmission gates is coupled to both first...
A high density, high speed, and low power circuit scheme is presented for vector switching port applications for advanced IC design. Embodiments exhibit superior...
US-6,442,099 Low power read scheme for memory array structures
A method and apparatus for consuming low power when accessing data from a memory array is provided. Further, a method and apparatus for consuming low power when...
US-6,441,656 Clock divider for analysis of all clock edges
A method for dividing a high frequency clock signal for analysis of all clock edges has been developed. The method includes receiving a high frequency clock...
US-6,441,640 CMOS-microprocessor chip and package anti-resonance pass-band shunt apparatus
A circuit for regulating resonance in a micro-chip has been developed. The circuit includes micro-chip supply voltage and a ground voltage, and a band-pass shunt...
US-6,441,595 Universal compact PCI pull-up/termination IC
A device for automatically providing variable resistance includes a comparator for comparing a reference voltage to an operating voltage, a first switch...
US-6,441,470 Technique to minimize crosstalk in electronic packages
The present invention is a technique to minimize crosstalk in multilayer IC packages. According to one or more embodiments of the present invention, signal...
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