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Patent # Description
US-6,583,263 Acrylated maleic-modified rosin esters and methods of preparing same
A two-step method for introducing acrylic functions into high molecular weight natural resins, under mild conditions, without the risk of gellation, wherein an...
US-6,583,001 Method for introducing an equivalent RC circuit in a MOS device using resistive paths
A method for providing low power MOS devices that include resistive paths specifically designed to provide a specified resistance between the bulk material of...
US-6,581,388 Active temperature gradient reducer
An apparatus and method for actively reducing the temperature gradient of a substrate. The substrate is placed in thermal contact with a heat dissipation...
US-D476,324 Server enclosure
US-D476,308 Radio
US-6,581,206 Computer program language subset validation
Language subset validation includes validating multiple program modules that comprise a program. The program modules include multiple bytecodes defined for a...
US-6,581,200 Abstracting netlist to manage routing information
A method of designing an integrated circuit, by generating a first netlist for a first router design tool, abstracting the first netlist to mask selected old...
US-6,581,192 Method and system for providing a heuristic approach for testing cell libraries
Method and system for testing building blocks or cells stored in cell libraries used in digital design including generating a test design configuration of rows...
US-6,581,094 Apparatus and method for identifying a digital device based on the device's uniform device descriptor file that...
A method executed by one or more digital devices operating in a networked environment includes the step of storing a network address for each digital device of a...
US-6,581,077 Method and apparatus for storing short-lived objects in a virtual machine
One embodiment of the mechanism provides a system for storing short-lived objects defined within an object-oriented programming system. These short-lived objects...
US-6,581,044 Method and apparatus for encoding license parameters within a license number for authentication purposes
A system that generates a license number based upon license parameters so that the license number can be authenticated by establishing that the license number...
US-6,581,018 Multiplexer select line exclusivity check method and apparatus
Disclosed herein is a system and method for determining whether multiplexers select lines within a circuit are exclusive of one another. The disclosed invention...
US-6,580,722 Bypassing topological restrictions with tunnels
Data units are tunneled through topological restrictions that reside in a path between a first network device and a second network device. For example, a remote...
US-6,580,303 Datapath control circuit with adjustable delay elements
A control circuit for a FIFO datapath is described. The control circuit consists of a chain of Muller C-elements with adjustable delay elements placed between...
US-6,579,518 Ceramic deodorizer
Disclosed is a deodorizer composition comprising magnesium and calcium phosphate compounds, capable of effectively removing various malodorous components from...
US-6,578,233 Hinge mechanism for outdoor lighting assembly
A hinge mechanism for a lighting assembly has a base with a slot, a shuttle guide extending from edges of the slot, a shuttle coupled with the base and capable...
US-D475,990 Radio
US-D475,983 Spacing frame device for electric facilities
US-6,578,178 Designing integrated circuits to reduce electromigration effects
A method of designing an integrated circuit calculates the current density in each metal lead. The method can calculates a mean time to failure for at least one...
US-6,578,168 Method for operating a boundary scan cell design for high performance I/O cells
A boundary scan cell design which places the multiplexor before the functional flip-flip on the functional line path, reducing the multiplexor delay in the...
US-6,578,166 Restricting the damaging effects of software faults on test and configuration circuitry
A system that restricts the damaging effects of software faults that interact with test and configuration circuitry. This test and configuration circuitry...
US-6,578,137 Branch and return on blocked load or store
A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or...
US-6,578,111 Cache memory system and method for managing streaming-data
A system and method are provided for efficient handling of streaming-data in a cache memory system (105) having a cache with several cache-lines (160) capable of...
US-6,578,071 Repeater for use in a shared memory computing system
A symmetrical multiprocessing system includes a plurality of nodes interconnected by a hierarchical bus. To allow for the transfer of data between nodes and to...
US-6,578,044 Method and system for typesafe attribute matching
A database system wherein one or more entry databases store a plurality of entries. Each entry is of a given type that defines the fields of the entry. Each...
US-6,578,036 Mechanism for performing polling in a system
An improved mechanism for efficiently polling file descriptors in a large scale computer system is disclosed. The polling of the file descriptors is performed by...
US-6,578,033 System and method for accessing a shared computer resource using a lock featuring different spin speeds...
A probabilistic queue lock divides requesters for a lock into at least three sets. In one embodiment, the requesters are divided into the owner of the lock, the...
US-6,577,628 Providing quality of service (QoS) in a network environment in which client connections are maintained for...
A method and apparatus are provided for implementing Quality of Service (QoS) in a network environment in which client connections are maintained for limited...
US-6,577,599 Small-scale reliable multicasting
A method and apparatus for efficient and reliable multicasting in a network environment. In embodiments of the invention, a sender transmits identical ...
US-6,577,498 Fully integrated computer racking system
A fully integrated computer rack mount system comprising: at least one shelving unit configured to store computers; at least one electrical panel coupled to at...
US-6,577,312 Graphics system configured to filter samples using a variable support filter
A computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders samples...
US-6,577,002 180 degree bump placement layout for an integrated circuit power grid
A 180 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and...
US-6,575,419 Universal support system for displays
The disclosed system is directed towards a universal support system. The universal support system comprises a pair of arched bases and an arched beam coupled to...
US-D475,661 Bottom frame of walker
US-6,574,768 Technique for correcting single-bit errors and detecting paired double-bit errors
A technique to detect and correct single bit errors and to detect paired bit errors in a data block. Two bits of the data block are paired and transferred on the...
US-6,574,746 System and method for improving multi-bit error protection in computer memory systems
A system and method for storing error correction check words in computer memory modules. Check bits stored in physically adjacent locations within a dynamic...
US-6,574,713 Heuristic for identifying loads guaranteed to hit in processor cache
A heuristic algorithm which identifies loads guaranteed to hit the processor cache which further provides a "minimal" set of prefetches which are...
US-6,574,695 System and method for providing hot swap capability using existing circuits and drivers with minimal changes
A system and method for providing hot swap capability with minimal changes in a system which uses existing circuitry and drivers. In one embodiment, a computer...
US-6,574,690 Asynchronous pulse bifurcator circuit with a bifurcation path coupled to control fifo and first and second...
A bifurcation circuit uses dynamic asP* protocol. to exchange data among three or more FIFOs. Each FIFO contains a plurality of places containing data and a...
US-6,574,659 Methods and apparatus for a directory-less memory access protocol in a distributed shared memory computer system
A method in a computer network having a first plurality of nodes coupled to a common network infrastructure and a distributed shared memory distributed among the...
US-6,574,160 Mechanism to minimize failure in differential sense amplifiers
According to one embodiment, a memory is disclosed. The memory includes a differential sense amplifier that receives a data input and a complementary data input;...
US-6,573,770 Programmable leakage current offset for delay locked loop
A method and apparatus for post-fabrication adjustment of a delay locked loop leakage current is provided. The adjustment system includes an adjustment circuit...
US-6,573,704 Method and apparatus for isolating an ambient air temperature sensor
A method and apparatus for thermally isolating a temperature sensor mounted on a printed circuit board from a heat generating component mounted on the printed...
US-6,573,590 Integrated circuit package with EMI containment features
An integrated circuit package comprising EMI containment features. The EMI containment features include a first EMI containment configuration and a second EMI...
US-6,571,360 Cage for dynamic attach testing of I/O boards
A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while...
US-6,571,338 Maintaining packet security in a computer network
The present invention provides a method and apparatus for determining the trust worthiness of executable packets, e.g., internet applets, being transmitted...
US-6,571,319 Methods and apparatus for combining a plurality of memory access transactions
Instruction combining logic combines data from a plurality of write transactions before the data is written into main memory. In one embodiment, the instruction...
US-6,571,306 Bus request mechanism for bus master which is parked on a shared bus
A method and mechanism for arbitrating access to a bus. A client which is parked on a bus is allowed to gain access to the bus without having to go through...
US-6,571,289 Chained registrations for mobile IP
A method for negotiating access to a private network for a mobile node that has migrated beyond the private network. A plurality of tunnel segments are composed...
US-6,571,232 System and method for browsing database schema information
A query object generator tool which generates interface definitions and code that implement a query object also generates a database schema access query object...
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