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Patent # Description
US-6,768,344 Clocked half-rail differential logic with single-rail logic and sense amplifier
Clocked half-rail differential logic circuits with single-rail logic and sense amplifier of the invention do not include complementary logic elements. According...
US-6,768,343 Clocked half-rail differential logic with sense amplifier and shut-off
Clocked half-rail differential logic circuits with sense amplifier and shut-off are activated by a delayed clock and include a sense amplifier circuit that is...
US-6,768,341 Synchronizing interface device for computer facilities
A computer facility includes a synchronizing interface device coupled between a high and a low speed processing devices for allowing the processing devices...
US-6,768,195 Multi-chip semiconductor device
The present invention relates to semiconductor devices, including multi-chip semiconductor devices, and methods of coupling semiconductor devices. In a...
US-6,768,072 Multi-directional grip switch lamp socket
A multi-directional switch grip includes an insulating body, a lamp socket and an insulating disc positioned between the insulating body and the lamp socket. A...
US-6,767,397 Methods for production of pigment dispersion
Disclosed is a process for the preparation of a pigment dispersion starting with a tank flushed pigment that is continuously fed into a twin screw extruder,...
US-6,767,186 Fan with automatic failure mode
An airflow apparatus (e.g., a fan, a blower) is provided for impeding or facilitating airflow through a channel when the apparatus is inoperative. The apparatus...
US-D493,347 Handle
US-6,766,521 Dataflow algorithm for symbolic computation of lowest upper bound type
A method, computer program, signal transmission, apparatus and system verify instructions in a module of a computer program to be dynamically linked with at...
US-6,766,517 System and method for facilitating thread-safe message passing communications among threads in respective processes
A system for facilitating thread-safe message passing communications among threads in respective processes includes arrangements for coordinating collective...
US-6,766,484 Method and apparatus for fully characterizing propagation delay through an n-input circuit
One embodiment of the present invention provides a system that facilitates fully characterizing propagation delay through an n-input circuit. The system operates...
US-6,766,477 Distributed component testing in an enterprise computer system
A method of automatically performing a component test at any number of locations in a distributed environment is disclosed. In general, in order to assure...
US-6,766,464 Method and apparatus for deskewing multiple incoming signals
An apparatus and method for compensating skew across a plurality of data interfaces includes using a recovered clock signal at an incoming clock rate to regulate...
US-6,766,432 Memory management system supporting object deletion in non-volatile memory
One embodiment of the present invention provides a system for freeing memory within a computing device. During operation, the system receives a command to free a...
US-6,766,428 Method and apparatus for storing prior versions of modified values to facilitate reliable execution
One embodiment of the present invention provides a system that facilitates reliable execution in a computer system by keeping track of write operations to a main...
US-6,766,349 Mechanism for obtaining a thread from, and returning a thread to, a thread pool without attaching and detaching
A JAVA application is typically executed as follows. First, a thread from a thread pool is attached to the JAVA virtual machine (JVM). Then, that thread is used...
US-6,766,342 System and method for computing and unordered Hadamard transform
A system and method for parallel computation of the unordered Hadamard transform. The computing system includes a plurality of interconnected processors and...
US-6,766,264 Method and apparatus for calibrating parameters to be used in a digital circuit simulation
One embodiment of the present invention provides a system for calibrating a model of a digital circuit to account for noise effects between signal lines. The...
US-6,765,571 Using a master controller to manage threads and resources for scene-based rendering
A system and method for rapid processing of scene-graph-based data and/or programs is disclosed. In one embodiment, the system may be configured to utilize a...
US-6,765,415 Clocked full-rail differential logic with shut-off
Clocked full-rail differential logic circuits with shut-off include a shut-off device. The addition of the shut-off device provides a full-rail differential...
US-6,765,410 Method and apparatus for performing a hazard-free multi-bit comparison
An exclusive OR (XOR) circuit is provided to perform a logical XOR function on multiple bits that eliminates the XOR function hazard. The XOR circuit performs a...
US-6,765,040 Publication gravure printing inks based on silicone modified water-based emulsions
The present invention relates an improved silicone modified water-based emulsion used primarily for publication gravure ink. Publication gravure water-based ink...
US-6,764,321 Ground potential only adaptor
There is described a servicing connection for connecting an electrical device to a supply outlet, wherein live and neutral contacts of the supply outlet are...
US-6,763,517 Automated analysis of kernel and user core files including searching, ranking, and recommending patch files
A computerized method for automatically analyzing a core file created by a computer system after an unexpected interrupt. The packages installed on the computer...
US-6,763,512 Detailed method for routing connections using tile expansion techniques and associated methods for designing...
Disclosed herein is a method and associated apparatus for the design and manufacture of VLSI circuit which incorporates therein a method for routing connections...
US-6,763,509 Method and apparatus for allocating decoupling capacitor cells
A method for allocating decoupling capacitor cells in an integrated circuit (IC) design, includes (a) obtaining geometrical information of rectangular areas in...
US-6,763,503 Accurate wire load model
A method for creating a wire load model using specific interconnect configuration information is provided. Further, a program that creates a wire load model by...
US-6,763,502 Method and system for searching a microelectronic device physical layout
Search functions of a physical layout tool are performed by converting a given physical layout name and selected searching layout names from string ...
US-6,763,479 High availability networking with alternate pathing failover
A method and mechanism operating within the Application layer of the architectural model for maintaining high availability in a two node computer network which...
US-6,763,468 Method and apparatus for authenticating users
A method and apparatus for authenticating users. Prior art mechanisms require each individual application (running on an "application server") that the user is...
US-6,763,440 Garbage collection using nursery regions for new objects in a virtual heap
A method and system for garbage collecting a virtual heap using nursery regions for newly created objects to reduce flushing of objects from an in-memory heap to...
US-6,763,397 Fully lazy linking
A method, computer program, signal transmission, apparatus and system for fully lazy verification of instructions in a module of a computer program include first...
US-6,763,382 Method and apparatus for demand based paging algorithm
A method of demand based retrieval of a data file including pages of data, in a network system having a remote host system interconnected to at least one local...
US-6,763,321 Method and apparatus to facilitate measurement of quality-of-service performance of a network server
One embodiment of the present invention provides a system that facilitates measuring quality-of-service of a computer network server or collection of servers by...
US-6,763,133 Moire image capturing apparatus and method therefor
The present invention relates a moire image capturing apparatus and the related method, the apparatus comprising: an optical projection unit arranged in...
US-6,762,961 Variable delay compensation for data-dependent mismatch in characteristic of opposing devices of a sense amplifier
Post-manufacture variation of timing may be employed to address data-dependent degradation or creep in device characteristics affecting a differential circuit....
US-6,762,934 Module ejection mechanism
An ejector mechanism is provided for a field replaceable module (e.g., a server blade) of modular computer system (e.g., a blade server system). The field...
US-6,762,798 Methods and apparatus for providing video control for television applications
Methods and apparatus for creating and manipulating a video window on a display associated with a television are disclosed. A set of parameters identifying a...
US-6,762,760 Graphics system configured to implement fogging based on radial distances
A graphics system configured to implement fogging according to an improved method based on radial distances. The amount of fog applied varies based on a...
US-6,762,623 High-resolution single-ended source-synchronous receiver
Disclosed are novel methods and apparatus for efficiently providing high-resolution single-ended source synchronous receivers. In an embodiment of the present...
US-6,762,505 150 degree bump placement layout for an integrated circuit power grid
A 150 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and...
US-D492,957 Hand stamp
US-6,760,907 Code generation for a bytecode compiler
A method, system and apparatus for generating and optimizing native code in a runtime compiler from a group of bytecodes presented to the compiler. The compiler...
US-6,760,891 Simulator of dynamic circuit for silicon critical path debug
An abstract register transfer level (RTL) model that simulates behavior of a dynamic circuit is created. The model is built upon an existing RTL with another...
US-6,760,868 Diagnostic cage for testing redundant system controllers
A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without...
US-6,760,815 Caching mechanism for a virtual heap
A caching mechanism for a virtual persistent heap is described. A feature of a virtual persistent heap is the method used to cache portions of the virtual...
US-6,760,786 Multiprocessing system configured to perform efficient block copy operations
A computer system optimized for block copy operations is provided. In order to perform a block copy from a remote source block to a local destination block, a...
US-6,760,736 Methods and systems for distributed failure detection and recovery using leasing techniques
A system for using a lease to detect a failure and to perform failure recovery is provided in using this system, a client requests a lease from a server to...
US-6,760,637 Method for interconnecting modular computer system components
A method capable of interconnecting modular computer system components includes attaching a secondary chassis to a primary chassis, attaching a motherboard to an...
US-6,760,442 Method and apparatus for adjusting the quality of digital media
A method and system are disclosed for adjusting the resolution or performance of digital media in a reversible manner. A mask component having a length of a...
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